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Message-Id: <f6e1858c-a31f-4f07-96ed-fb1d792dab49@www.fastmail.com>
Date: Sat, 15 Jan 2022 22:25:58 +0000
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Laurent Vivier" <laurent@...ier.eu>, linux-kernel@...r.kernel.org
Cc: "John Stultz" <john.stultz@...aro.org>, linux-rtc@...r.kernel.org,
"Daniel Lezcano" <daniel.lezcano@...aro.org>,
"Thomas Gleixner" <tglx@...utronix.de>,
"Alessandro Zummo" <a.zummo@...ertech.it>,
"Alexandre Belloni" <alexandre.belloni@...tlin.com>,
"Stephen Boyd" <sboyd@...nel.org>,
"Geert Uytterhoeven" <geert@...ux-m68k.org>,
"Arnd Bergmann" <arnd@...db.de>, linux-m68k@...ts.linux-m68k.org
Subject: Re: [PATCH v8 2/4] rtc: goldfish: introduce
goldfish_ioread32()/goldfish_iowrite32()
在2022年1月15日一月 下午7:32，Laurent Vivier写道：
> The goldfish device always uses the same endianness as the architecture
> using it:
> https://android.googlesource.com/platform/external/qemu/+/refs/heads/emu-master-dev/hw/timer/goldfish_timer.c#177
>
> On a big-endian machine, the device is also big-endian, on a
> little-endian machine the device is little-endian.
>
> So we need to use the right accessor to read/write values to the goldfish
> registers: ioread32()/iowrite32() on a little-endian machine,
> ioread32be()/iowrite32be() on a big-endian machine.
>
> This patch introduces goldfish_ioread32()/goldfish_iowrite32() that uses
> the expected accessor according to the machine endianness.
>
> Signed-off-by: Laurent Vivier <laurent@...ier.eu>
Acked-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> ---
> drivers/rtc/rtc-goldfish.c | 39 +++++++++++++++++++++++---------------
> 1 file changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/rtc/rtc-goldfish.c b/drivers/rtc/rtc-goldfish.c
> index 7ab95d052644..b0cae4729b03 100644
> --- a/drivers/rtc/rtc-goldfish.c
> +++ b/drivers/rtc/rtc-goldfish.c
> @@ -23,6 +23,15 @@
> #define TIMER_ALARM_STATUS 0x18
> #define TIMER_CLEAR_INTERRUPT 0x1c
>
> +/* goldfish endianness depends on CPU endianness */
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +#define goldfish_ioread32 ioread32be
> +#define goldfish_iowrite32 iowrite32be
> +#else
> +#define goldfish_ioread32 ioread32
> +#define goldfish_iowrite32 iowrite32
> +#endif
> +
> struct goldfish_rtc {
> void __iomem *base;
> int irq;
> @@ -41,8 +50,8 @@ static int goldfish_rtc_read_alarm(struct device *dev,
> rtcdrv = dev_get_drvdata(dev);
> base = rtcdrv->base;
>
> - rtc_alarm_low = readl(base + TIMER_ALARM_LOW);
> - rtc_alarm_high = readl(base + TIMER_ALARM_HIGH);
> + rtc_alarm_low = goldfish_ioread32(base + TIMER_ALARM_LOW);
> + rtc_alarm_high = goldfish_ioread32(base + TIMER_ALARM_HIGH);
> rtc_alarm = (rtc_alarm_high << 32) | rtc_alarm_low;
>
> do_div(rtc_alarm, NSEC_PER_SEC);
> @@ -50,7 +59,7 @@ static int goldfish_rtc_read_alarm(struct device *dev,
>
> rtc_time64_to_tm(rtc_alarm, &alrm->time);
>
> - if (readl(base + TIMER_ALARM_STATUS))
> + if (goldfish_ioread32(base + TIMER_ALARM_STATUS))
> alrm->enabled = 1;
> else
> alrm->enabled = 0;
> @@ -71,18 +80,18 @@ static int goldfish_rtc_set_alarm(struct device *dev,
>
> if (alrm->enabled) {
> rtc_alarm64 = rtc_tm_to_time64(&alrm->time) * NSEC_PER_SEC;
> - writel((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH);
> - writel(rtc_alarm64, base + TIMER_ALARM_LOW);
> - writel(1, base + TIMER_IRQ_ENABLED);
> + goldfish_iowrite32((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH);
> + goldfish_iowrite32(rtc_alarm64, base + TIMER_ALARM_LOW);
> + goldfish_iowrite32(1, base + TIMER_IRQ_ENABLED);
> } else {
> /*
> * if this function was called with enabled=0
> * then it could mean that the application is
> * trying to cancel an ongoing alarm
> */
> - rtc_status_reg = readl(base + TIMER_ALARM_STATUS);
> + rtc_status_reg = goldfish_ioread32(base + TIMER_ALARM_STATUS);
> if (rtc_status_reg)
> - writel(1, base + TIMER_CLEAR_ALARM);
> + goldfish_iowrite32(1, base + TIMER_CLEAR_ALARM);
> }
>
> return 0;
> @@ -98,9 +107,9 @@ static int goldfish_rtc_alarm_irq_enable(struct device *dev,
> base = rtcdrv->base;
>
> if (enabled)
> - writel(1, base + TIMER_IRQ_ENABLED);
> + goldfish_iowrite32(1, base + TIMER_IRQ_ENABLED);
> else
> - writel(0, base + TIMER_IRQ_ENABLED);
> + goldfish_iowrite32(0, base + TIMER_IRQ_ENABLED);
>
> return 0;
> }
> @@ -110,7 +119,7 @@ static irqreturn_t goldfish_rtc_interrupt(int irq,
> void *dev_id)
> struct goldfish_rtc *rtcdrv = dev_id;
> void __iomem *base = rtcdrv->base;
>
> - writel(1, base + TIMER_CLEAR_INTERRUPT);
> + goldfish_iowrite32(1, base + TIMER_CLEAR_INTERRUPT);
>
> rtc_update_irq(rtcdrv->rtc, 1, RTC_IRQF | RTC_AF);
>
> @@ -128,8 +137,8 @@ static int goldfish_rtc_read_time(struct device
> *dev, struct rtc_time *tm)
> rtcdrv = dev_get_drvdata(dev);
> base = rtcdrv->base;
>
> - time_low = readl(base + TIMER_TIME_LOW);
> - time_high = readl(base + TIMER_TIME_HIGH);
> + time_low = goldfish_ioread32(base + TIMER_TIME_LOW);
> + time_high = goldfish_ioread32(base + TIMER_TIME_HIGH);
> time = (time_high << 32) | time_low;
>
> do_div(time, NSEC_PER_SEC);
> @@ -149,8 +158,8 @@ static int goldfish_rtc_set_time(struct device
> *dev, struct rtc_time *tm)
> base = rtcdrv->base;
>
> now64 = rtc_tm_to_time64(tm) * NSEC_PER_SEC;
> - writel((now64 >> 32), base + TIMER_TIME_HIGH);
> - writel(now64, base + TIMER_TIME_LOW);
> + goldfish_iowrite32((now64 >> 32), base + TIMER_TIME_HIGH);
> + goldfish_iowrite32(now64, base + TIMER_TIME_LOW);
>
> return 0;
> }
> --
> 2.34.1
--
- Jiaxun
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