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Message-ID: <1fa23a4d-f647-c3ae-df8c-4cbd91f5a4c6@gmail.com>
Date: Tue, 18 Jan 2022 12:37:51 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Sasha Levin <sashal@...nel.org>, linux-kernel@...r.kernel.org,
stable@...r.kernel.org
Cc: Maxim Schwalm <maxim.schwalm@...il.com>,
Thierry Reding <treding@...dia.com>, thierry.reding@...il.com,
airlied@...ux.ie, daniel@...ll.ch, jonathanh@...dia.com,
dri-devel@...ts.freedesktop.org, linux-tegra@...r.kernel.org
Subject: Re: [PATCH AUTOSEL 5.15 123/188] drm/tegra: dc: rgb: Allow changing
PLLD rate on Tegra30+
18.01.2022 05:30, Sasha Levin пишет:
> From: Dmitry Osipenko <digetx@...il.com>
>
> [ Upstream commit 0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c ]
>
> Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI
> bridge that requires a precise clock rate in order to operate properly.
> Tegra30 has a dedicated PLL for each display controller, hence the PLL
> rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB
> output. Configure the clock rate before display controller is enabled
> since DC itself may be running off this PLL and it's not okay to change
> the rate of the active PLL that doesn't support dynamic frequency
> switching since hardware will hang.
>
> Tested-by: Maxim Schwalm <maxim.schwalm@...il.com> #TF700T
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> Signed-off-by: Thierry Reding <treding@...dia.com>
> Signed-off-by: Sasha Levin <sashal@...nel.org>
> ---
> drivers/gpu/drm/tegra/dc.c | 27 ++++++++++++--------
> drivers/gpu/drm/tegra/dc.h | 1 +
> drivers/gpu/drm/tegra/rgb.c | 49 +++++++++++++++++++++++++++++++++++--
> 3 files changed, 65 insertions(+), 12 deletions(-)
Hi,
This patch shouldn't be ported to any stable kernel because h/w that
needs this patch was just merged to the 5.17.
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