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Message-Id: <20220118012051.21691-22-ansuelsmth@gmail.com>
Date: Tue, 18 Jan 2022 02:20:51 +0100
From: Ansuel Smith <ansuelsmth@...il.com>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Ansuel Smith <ansuelsmth@...il.com>
Subject: [PATCH 17/17] ARM: dts: qcom: add ipq8065 dtsi
Many device are based on ipq8065 SoC. Ipq8065 is an evolution of the
ipq8064 SoC (also named ipq8064-v3.0 from qsdk) that has all the
improvement from ipq8064-v2.0 with the addition of a more powerful CPU
that can now be clocked to 1.7Ghz, a quicker L2 cache that can be
clocked to 1.4Ghz. It also shipped with more powerful regulators to
provide the required voltage to the CPUs and L2.
Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
---
arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 ++++++++++++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi
new file mode 100644
index 000000000000..817d723b0c88
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm IPQ8065";
+ compatible = "qcom,ipq8065", "qcom,ipq8064";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@...00000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@...40000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&smb208_s2a {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&smb208_s2b {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&opp_table_l2 {
+ /delete-node/opp-1200000000;
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
+
+&opp_table0 {
+ /*
+ * On ipq8065 1.2 ghz freq is not present
+ * Remove it to make cpufreq work and not
+ * complain for missing definition
+ */
+
+ /delete-node/opp-1200000000;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
+ opp-level = <1>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
--
2.33.1
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