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Message-Id: <20220118053950.2605-1-yuji2.ishikawa@toshiba.co.jp>
Date: Tue, 18 Jan 2022 14:39:48 +0900
From: Yuji Ishikawa <yuji2.ishikawa@...hiba.co.jp>
To: "David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>
Cc: Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...com>,
Jose Abreu <joabreu@...opsys.com>, netdev@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
nobuhiro1.iwamatsu@...hiba.co.jp, yuji2.ishikawa@...hiba.co.jp
Subject: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
Hi,
This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
It is composed of two parts:
* 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
* 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Best regards,
Yuji
Yuji Ishikawa (2):
net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++-------
1 file changed, 26 insertions(+), 16 deletions(-)
--
2.17.1
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