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Message-ID: <1b6a8366-d1ab-536f-9bad-8c2b7a822fcb@intel.com>
Date:   Wed, 19 Jan 2022 07:23:05 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     Like Xu <like.xu.linux@...il.com>,
        Paolo Bonzini <pbonzini@...hat.com>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        Sean Christopherson <seanjc@...gle.com>,
        Jim Mattson <jmattson@...gle.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Joerg Roedel <joro@...tes.org>, x86@...nel.org,
        kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Like Xu <likexu@...cent.com>
Subject: Re: [PATCH] KVM: x86/xcr0: Don't make XFEATURE_MASK_SSE a mandatory
 bit setting

On 1/18/22 11:04 PM, Like Xu wrote:
> Remove the XFEATURE_MASK_SSE bit as part of the XFEATURE_MASK_EXTEND
> and opportunistically, move it into the context of its unique user KVM.

Is this a problem for xstate_required_size()?  The rules for the CPUID
sub-functions <=1 are different than those for >1.  Most importantly,
'eax' doesn't enumerate the size of the feature for the XFEATURE_SSE
sub-leaf.

I think XFEATURE_MASK_EXTEND was being used to avoid that oddity:

> u32 xstate_required_size(u64 xstate_bv, bool compacted)
> {
>         int feature_bit = 0;
>         u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
> 
>         xstate_bv &= XFEATURE_MASK_EXTEND;
>         while (xstate_bv) {
>                 if (xstate_bv & 0x1) {
>                         u32 eax, ebx, ecx, edx, offset;
>                         cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
>                         /* ECX[1]: 64B alignment in compacted form */
>                         if (compacted)
>                                 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
>                         else
>                                 offset = ebx;
>                         ret = max(ret, offset + eax);
>                 }
> 
>                 xstate_bv >>= 1;
>                 feature_bit++;
>         }
> 
>         return ret;
> }

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