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Message-Id: <20220119203133.467264-4-bhupesh.sharma@linaro.org>
Date: Thu, 20 Jan 2022 02:01:32 +0530
From: Bhupesh Sharma <bhupesh.sharma@...aro.org>
To: linux-arm-msm@...r.kernel.org
Cc: bhupesh.sharma@...aro.org, bhupesh.linux@...il.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
robh+dt@...nel.org, linux-gpio@...r.kernel.org,
linus.walleij@...aro.org, bjorn.andersson@...aro.org,
Vinod Koul <vkoul@...nel.org>, Rob Herring <robh@...nel.org>
Subject: [PATCH 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node
Add pdc interrupt controller for sm8150.
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>
Cc: Rob Herring <robh@...nel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 6012322a5984..cc4dc11b2585 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1626,6 +1626,16 @@ system-cache-controller@...0000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ pdc: interrupt-controller@...0000 {
+ compatible = "qcom,sm8150-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
ufs_mem_hc: ufshc@...4000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.33.1
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