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Message-ID: <CAHp75VcGmmRpRD99tFHd7WOPs6uyz3uWuTEoc=G+VmbPYAUvuA@mail.gmail.com>
Date: Thu, 20 Jan 2022 13:28:09 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Terry Bowman <terry.bowman@....com>
Cc: Guenter Roeck <linux@...ck-us.net>, linux-watchdog@...r.kernel.org,
Jean Delvare <jdelvare@...e.com>,
linux-i2c <linux-i2c@...r.kernel.org>,
Wolfram Sang <wsa@...nel.org>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Robert Richter <rrichter@....com>,
Tom Lendacky <thomas.lendacky@....com>,
sudheesh.mavila@....com,
"Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@....com>,
Basavaraj Natikar <Basavaraj.Natikar@....com>,
Shyam Sundar S K <Shyam-sundar.S-k@....com>,
Mario Limonciello <Mario.Limonciello@....com>
Subject: Re: [PATCH v3 8/9] i2c: piix4: Add EFCH MMIO support for SMBus port select
On Thu, Jan 20, 2022 at 1:08 AM Terry Bowman <terry.bowman@....com> wrote:
>
> AMD processors include registers capable of selecting between 2 SMBus
> ports. Port selection is made during each user access by writing to
> FCH::PM::DECODEEN[smbus0sel]. Change the driver to use MMIO during
> SMBus port selection because cd6h/cd7h port I/O is not available on
> later AMD processors.
...
> }
> +
> /*
Stray change.
--
With Best Regards,
Andy Shevchenko
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