lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <1642699582-14785-5-git-send-email-quic_c_sbhanu@quicinc.com>
Date:   Thu, 20 Jan 2022 22:56:22 +0530
From:   Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
To:     adrian.hunter@...el.com, quic_asutoshd@...cinc.com,
        ulf.hansson@...aro.org, agross@...nel.org,
        bjorn.andersson@...aro.org, linux-mmc@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     stummala@...eaurora.org, vbadigan@...eaurora.org,
        quic_rampraka@...cinc.com, quic_pragalla@...cinc.com,
        sartgarg@...eaurora.org, nitirawa@...eaurora.org,
        sayalil@...eaurora.org,
        Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>,
        Liangliang Lu <luliang@...eaurora.org>,
        "Bao D . Nguyen" <nguyenb@...eaurora.org>
Subject: [PATCH V3 4/4] mmc: cqhci: Capture eMMC and SD card errors

Add changes to capture eMMC and SD card errors.
This is useful for debug and testing.

Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
Signed-off-by: Liangliang Lu <luliang@...eaurora.org>
Signed-off-by: Sayali Lokhande <sayalil@...eaurora.org>
Signed-off-by: Bao D. Nguyen <nguyenb@...eaurora.org>
Signed-off-by: Ram Prakash Gupta <quic_rampraka@...cinc.com>
---
 drivers/mmc/host/cqhci-core.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c
index b0d30c3..2908d30 100644
--- a/drivers/mmc/host/cqhci-core.c
+++ b/drivers/mmc/host/cqhci-core.c
@@ -822,8 +822,15 @@ irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
 	pr_debug("%s: cqhci: IRQ status: 0x%08x\n", mmc_hostname(mmc), status);
 
 	if ((status & (CQHCI_IS_RED | CQHCI_IS_GCE | CQHCI_IS_ICCE)) ||
-	    cmd_error || data_error)
+	    cmd_error || data_error) {
+		if ((status & CQHCI_IS_RED) && mmc->err_stats_enabled)
+			mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_RED);
+		if ((status & CQHCI_IS_GCE) && (mmc->err_stats_enabled))
+			mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_GCE);
+		if ((status & CQHCI_IS_ICCE) && mmc->err_stats_enabled)
+			mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_ICCE);
 		cqhci_error_irq(mmc, status, cmd_error, data_error);
+	}
 
 	if (status & CQHCI_IS_TCC) {
 		/* read TCN and complete the request */
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ