linux-kernel - Re: [PATCH RESEND v2 4/5] ARM: dts: sti: add the PCIe controller node within stih407-family

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Message-ID: <6d45806f-d8f0-dabd-ae65-a820c1880ed4@foss.st.com>
Date:   Mon, 24 Jan 2022 13:47:40 +0100
From:   Patrice CHOTARD <patrice.chotard@...s.st.com>
To:     Alain Volmat <avolmat@...com>, Rob Herring <robh+dt@...nel.org>,
        <linux-pci@...r.kernel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        Fabrice Gasnier <fabrice.gasnier@...s.st.com>
Subject: Re: [PATCH RESEND v2 4/5] ARM: dts: sti: add the PCIe controller node
 within stih407-family

Hi Alain

On 1/3/22 08:47, Alain Volmat wrote:
> Add the pcie1 entry within stih407-family dtsi.
> 
> Signed-off-by: Alain Volmat <avolmat@...com>
> ---
>  arch/arm/boot/dts/stih407-family.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
> index 21f3347a91d6..fe4ea2d5b583 100644
> --- a/arch/arm/boot/dts/stih407-family.dtsi
> +++ b/arch/arm/boot/dts/stih407-family.dtsi
> @@ -631,6 +631,46 @@ spifsm: spifsm@...2000{
>  			status = "disabled";
>  		};
>  
> +		pcie1: pcie@...0000 {
> +			compatible = "st,stih407-pcie";
> +			device_type = "pci";
> +			reg = <0x09b10000 0x00001000>,	/* cntrl registers */
> +			      <0x3fff0000 0x00010000>,	/* config space */
> +			      <0x40000000 0xc0000000>;	/* lmi mem window */
> +
> +			reg-names = "dbi",
> +				    "config",
> +				    "mem-window";
> +
> +			st,syscfg = <&syscfg_core 0xdc 0xe4>;
> +
> +			#interrupt-cells = <1>;
> +			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi";
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			/* non-prefetchable and prefetchable */
> +			ranges = <0x82000000 0 0x30000000 0x30000000 0 0x05550000>,
> +				 <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>;
> +			bus-range = <0x00 0xff>;
> +
> +			resets = <&softreset STIH407_PCIE1_SOFTRESET>,
> +				 <&powerdown STIH407_PCIE1_POWERDOWN>;
> +
> +			reset-names = "softreset", "powerdown";
> +
> +			phys = <&phy_port1 PHY_TYPE_PCIE>;
> +			phy-names = "pcie";
> +
> +			status = "disabled";
> +		};
> +
>  		sata0: sata@...0000 {
>  			compatible = "st,ahci";
>  			reg = <0x9b20000 0x1000>;
Reviewed-by: Patrice Chotard <patrice.chotard@...s.st.com>

Thanks
Patrice