linux-kernel - Re: [RFC V1 02/11] arm64/perf: Add register definitions for BRBE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <877dap8c0o.wl-maz@kernel.org>
Date:   Mon, 24 Jan 2022 14:05:27 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Anshuman Khandual <anshuman.khandual@....com>
Cc:     linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        linux-perf-users@...r.kernel.org
Subject: Re: [RFC V1 02/11] arm64/perf: Add register definitions for BRBE

On Mon, 24 Jan 2022 04:30:44 +0000,
Anshuman Khandual <anshuman.khandual@....com> wrote:
> 
> This adds BRBE related register definitions and various other related field
> macros there in. These will be used subsequently in a BRBE driver which is
> being added later on.
> 
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: Marc Zyngier <maz@...nel.org>
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
> ---
>  arch/arm64/include/asm/sysreg.h | 216 ++++++++++++++++++++++++++++++++
>  1 file changed, 216 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 898bee0004ae..d8fd7e806a47 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -141,6 +141,218 @@
>  #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
>  #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
>  
> +/*
> + * BRBINF<N>_EL1 Encoding: [2, 1, 8, CRm, op2]
> + *
> + * derived as <CRm> = c{N<3:0>} <op2> = (N<4>x4 + 0)
> + */
> +#define SYS_BRBINF0_EL1			sys_reg(2, 1, 8, 0, 0)
> +#define SYS_BRBINF1_EL1			sys_reg(2, 1, 8, 1, 0)
> +#define SYS_BRBINF2_EL1			sys_reg(2, 1, 8, 2, 0)
> +#define SYS_BRBINF3_EL1			sys_reg(2, 1, 8, 3, 0)
> +#define SYS_BRBINF4_EL1			sys_reg(2, 1, 8, 4, 0)
> +#define SYS_BRBINF5_EL1			sys_reg(2, 1, 8, 5, 0)
> +#define SYS_BRBINF6_EL1			sys_reg(2, 1, 8, 6, 0)
> +#define SYS_BRBINF7_EL1			sys_reg(2, 1, 8, 7, 0)
> +#define SYS_BRBINF8_EL1			sys_reg(2, 1, 8, 8, 0)
> +#define SYS_BRBINF9_EL1			sys_reg(2, 1, 8, 9, 0)

[snip]

Since the architecture gives you the formula to build these, why do
you enumerate each and every register encoding? I'd rather see
something like:

#define __SYS_BRBINFO(n) sys_reg(2, 1, 8, ((n) & 0xf), (((n) & 0x10)) >> 2)
#define SYS_BRBINF0_EL1	__SYS_BRBINFO(0)
[...]

and something similar for all the new registers that come in packs of
32... We already have similar things for AMU, PMU, GIC and co.

Thanks,

	M.


-- 
Without deviation from the norm, progress is not possible.