linux-kernel - Re: [PATCH V3 0/7] coresight: trbe: Workaround Cortex-A510 erratas

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <8a348786-d028-a991-178f-60b17d3d6554@arm.com>
Date:   Tue, 25 Jan 2022 10:02:31 +0000
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Anshuman Khandual <anshuman.khandual@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Mathieu Poirier <mathieu.poirier@...aro.org>,
        coresight@...ts.linaro.org, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3 0/7] coresight: trbe: Workaround Cortex-A510 erratas

On 25/01/2022 03:21, Anshuman Khandual wrote:
> 
> 
> On 1/11/22 9:08 AM, Anshuman Khandual wrote:
>> 	This series adds three different workarounds in the TRBE driver for
>> Cortex-A510 specific erratas. But first, this adds Cortex-A510 specific cpu
>> part number definition in the platform. This series applies on 5.16.
>>
>> Relevant errata documents can be found here.
>>
>> https://developer.arm.com/documentation/SDEN2397239/900
>> https://developer.arm.com/documentation/SDEN2397589/900
>>
>> Changes in V3:
>>
>> - Moved the comment inside trbe_needs_drain_after_disable()
>> - Moved the comment inside trbe_needs_ctxt_sync_after_enable()
>>
>> Changes in V2:
>>
>> https://lore.kernel.org/all/1641517808-5735-1-git-send-email-anshuman.khandual@arm.com/
>>
>> Accommodated most review comments from the previous version.
>>
>> - Split all patches into CPU errata definition, detection and TRBE workarounds
>> - s/TRBE_WORKAROUND_SYSREG_WRITE_FAILURE/TRBE_NEEDS_DRAIN_AFTER_DISABLE
>> - s/TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE/TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE
>> - s/trbe_may_fail_sysreg_write()/trbe_needs_drain_after_disable()
>> - s/trbe_may_corrupt_with_enable()/trbe_needs_ctxt_sync_after_enable()
>> - Updated Kconfig help message for config ARM64_ERRATUM_1902691
>> - Updated error message for trbe_is_broken() detection
>> - Added new trblimitr parameter to set_trbe_enabled(), improving performance
>> - Added COMPILE_TEST dependency in the errata, until TRBE part is available
>>
>> Changes in V1:
>>
>> https://lore.kernel.org/lkml/1641359159-22726-1-git-send-email-anshuman.khandual@arm.com/
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will@...nel.org>
>> Cc: Mathieu Poirier <mathieu.poirier@...aro.org>
>> Cc: Suzuki Poulose <suzuki.poulose@....com>
>> Cc: coresight@...ts.linaro.org
>> Cc: linux-doc@...r.kernel.org
>> Cc: linux-arm-kernel@...ts.infradead.org
>> Cc: linux-kernel@...r.kernel.org
>>
>> Anshuman Khandual (7):
>>    arm64: Add Cortex-A510 CPU part definition
>>    arm64: errata: Add detection for TRBE ignored system register writes
>>    arm64: errata: Add detection for TRBE invalid prohibited states
>>    arm64: errata: Add detection for TRBE trace data corruption
>>    coresight: trbe: Work around the ignored system register writes
>>    coresight: trbe: Work around the invalid prohibited states
>>    coresight: trbe: Work around the trace data corruption
> 
> Hello Catalin/Mathieu,
> 
> I am wondering how this series is going to be merged i.e via arm64 or coresight
> tree ? Also will this require rebasing (and resend) against v5.17-rc1 release.
> Please do suggest. Thank you.

I would recommend rebasing on rc1.

Thanks
Suzuki