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Message-ID: <CAL_Jsq++-Sp45vna5-WhPsnrxp1_J1krrBUPgd2y3xkp5=sTSw@mail.gmail.com>
Date:   Wed, 26 Jan 2022 13:36:45 -0600
From:   Rob Herring <robh+dt@...nel.org>
To:     Anup Patel <anup@...infault.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Anup Patel <anup.patel@....com>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts

On Fri, Dec 17, 2021 at 6:48 AM Anup Patel <anup@...infault.org> wrote:
>
> On Fri, Dec 17, 2021 at 6:08 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> >
> > The number of interrupts lacks an upper bound, thus assuming one,
> > causing properly grouped "interrupts-extended" properties to be flagged
> > as an error by "make dtbs_check".
> >
> > Fix this by adding the missing "maxItems".  As the architectural maximum
> > is 4095 interrupts, using that as the limit would be unpractical.  Hence
> > limit it to 10 interrupts (two interrupts for a system management core,
> > and two interrupts per core for other cores).  This should be sufficient
> > for now, and the limit can always be increased when the need arises.
>
> Same comment as the PLIC DT binding patch.
>
> The "maxItems" should represent CLINT spec constraints so
> please don't add any synthetic value here.

I agree.

Geert, are you going to respin these?

Rob

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