linux-kernel - Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: Improve performance of busy bit polling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YfHdCDIUvpaYpDSF@lunn.ch>
Date:   Thu, 27 Jan 2022 00:45:12 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Tobias Waldekranz <tobias@...dekranz.com>
Cc:     davem@...emloft.net, kuba@...nel.org, netdev@...r.kernel.org,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: Improve performance of
 busy bit polling

> @@ -86,12 +86,12 @@ int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
>  int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
>  			u16 mask, u16 val)
>  {
> +	const unsigned long timeout = jiffies + msecs_to_jiffies(50);
>  	u16 data;
>  	int err;
> -	int i;
>  
>  	/* There's no bus specific operation to wait for a mask */
> -	for (i = 0; i < 16; i++) {
> +	do {
>  		err = mv88e6xxx_read(chip, addr, reg, &data);
>  		if (err)
>  			return err;
> @@ -99,8 +99,8 @@ int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
>  		if ((data & mask) == val)
>  			return 0;
>  
> -		usleep_range(1000, 2000);
> -	}
> +		cpu_relax();
> +	} while (time_before(jiffies, timeout));

I don't know if this is an issue or not...

There are a few bit-banging systems out there. For those, i wonder if
50ms is too short? With the old code, they had 16 chances, no matter
how slow they were. With the new code, if they take 50ms for one
transaction, they don't get a second chance.

But if they have taken 50ms, around 37ms has been spent with the
preamble, start, op, phy address, and register address. I assume at
that point the switch actually looks at the register, and given your
timings, it really should be ready, so a second loop is probably not
required?

O.K, so this seems safe.

     Andrew