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Message-ID: <CAMdYzYpkXdXDST+N8dEn7UvibXmytwNeJ+KZ9bn9Oq+RJuSaeQ@mail.gmail.com>
Date: Thu, 27 Jan 2022 18:32:13 -0500
From: Peter Geis <pgwipeout@...il.com>
To: Michael Riesch <michael.riesch@...fvision.net>
Cc: arm-mail-list <linux-arm-kernel@...ts.infradead.org>,
"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Nicolas Frattaroli <frattaroli.nicolas@...il.com>,
Liang Chen <cl@...k-chips.com>
Subject: Re: [PATCH 1/2] arm64: dts: rockchip: rename and sort the rk356x usb2
phy handles
On Thu, Jan 27, 2022 at 2:05 PM Michael Riesch
<michael.riesch@...fvision.net> wrote:
>
> All nodes and handles related to USB have the prefix usb or usb2,
> whereas the phy handles are prefixed with u2phy. Rename for
> consistency reasons and to facilitate sorting.
>
> This patch also updates the handles in the only board file that
> uses them (rk3566-quartz64-a.dts).
Good Evening,
While I'm not against this idea, my main concern still stands.
I spent a great deal of thought on this, and decided to go the route I
did to maintain consistency with previous generations.
As such, I see one of three paths here:
- Pull this patch only and depart rk356x from previous SoCs.
- Do the same for previous SoCs to maintain consistency.
- Drop this patch to maintain consistency with previous SoCs.
I ask that others weigh in here, as offline discussion has produced
mixed results already.
Thanks,
Peter
>
> Signed-off-by: Michael Riesch <michael.riesch@...fvision.net>
> ---
> .../boot/dts/rockchip/rk3566-quartz64-a.dts | 18 ++++++++---------
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 +++++++++----------
> 2 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> index f1d6bf10c650..3e65465ac7d5 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> @@ -574,32 +574,32 @@ &uart2 {
> status = "okay";
> };
>
> -&u2phy1_host {
> - phy-supply = <&vcc5v0_usb20_host>;
> +&usb_host0_ehci {
> status = "okay";
> };
>
> -&u2phy1_otg {
> - phy-supply = <&vcc5v0_usb20_host>;
> +&usb_host0_ohci {
> status = "okay";
> };
>
> -&u2phy1 {
> +&usb_host1_ehci {
> status = "okay";
> };
>
> -&usb_host0_ehci {
> +&usb_host1_ohci {
> status = "okay";
> };
>
> -&usb_host0_ohci {
> +&usb2phy1 {
> status = "okay";
> };
>
> -&usb_host1_ehci {
> +&usb2phy1_host {
> + phy-supply = <&vcc5v0_usb20_host>;
> status = "okay";
> };
>
> -&usb_host1_ohci {
> +&usb2phy1_otg {
> + phy-supply = <&vcc5v0_usb20_host>;
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 8ee2fab676f4..69c30992ced2 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -214,7 +214,7 @@ usb_host0_ehci: usb@...00000 {
> interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
> <&cru PCLK_USB>;
> - phys = <&u2phy1_otg>;
> + phys = <&usb2phy1_otg>;
> phy-names = "usb";
> status = "disabled";
> };
> @@ -225,7 +225,7 @@ usb_host0_ohci: usb@...40000 {
> interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
> <&cru PCLK_USB>;
> - phys = <&u2phy1_otg>;
> + phys = <&usb2phy1_otg>;
> phy-names = "usb";
> status = "disabled";
> };
> @@ -236,7 +236,7 @@ usb_host1_ehci: usb@...80000 {
> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
> <&cru PCLK_USB>;
> - phys = <&u2phy1_host>;
> + phys = <&usb2phy1_host>;
> phy-names = "usb";
> status = "disabled";
> };
> @@ -247,7 +247,7 @@ usb_host1_ohci: usb@...c0000 {
> interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
> <&cru PCLK_USB>;
> - phys = <&u2phy1_host>;
> + phys = <&usb2phy1_host>;
> phy-names = "usb";
> status = "disabled";
> };
> @@ -1195,7 +1195,7 @@ pwm15: pwm@...00030 {
> status = "disabled";
> };
>
> - u2phy0: usb2phy@...a0000 {
> + usb2phy0: usb2phy@...a0000 {
> compatible = "rockchip,rk3568-usb2phy";
> reg = <0x0 0xfe8a0000 0x0 0x10000>;
> clocks = <&pmucru CLK_USBPHY0_REF>;
> @@ -1206,18 +1206,18 @@ u2phy0: usb2phy@...a0000 {
> #clock-cells = <0>;
> status = "disabled";
>
> - u2phy0_host: host-port {
> + usb2phy0_host: host-port {
> #phy-cells = <0>;
> status = "disabled";
> };
>
> - u2phy0_otg: otg-port {
> + usb2phy0_otg: otg-port {
> #phy-cells = <0>;
> status = "disabled";
> };
> };
>
> - u2phy1: usb2phy@...b0000 {
> + usb2phy1: usb2phy@...b0000 {
> compatible = "rockchip,rk3568-usb2phy";
> reg = <0x0 0xfe8b0000 0x0 0x10000>;
> clocks = <&pmucru CLK_USBPHY1_REF>;
> @@ -1228,12 +1228,12 @@ u2phy1: usb2phy@...b0000 {
> #clock-cells = <0>;
> status = "disabled";
>
> - u2phy1_host: host-port {
> + usb2phy1_host: host-port {
> #phy-cells = <0>;
> status = "disabled";
> };
>
> - u2phy1_otg: otg-port {
> + usb2phy1_otg: otg-port {
> #phy-cells = <0>;
> status = "disabled";
> };
> --
> 2.30.2
>
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