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Message-ID: <20220127063145.13413-2-hui.liu@mediatek.com>
Date: Thu, 27 Jan 2022 14:31:44 +0800
From: Hui-Liu Liu <hui.liu@...iatek.com>
To: <lee.jones@...aro.org>, <robh+dt@...nel.org>,
<matthias.bgg@...il.com>, <lgirdwood@...il.com>,
<broonie@...nel.org>, <eddie.huang@...iatek.com>,
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<fshao@...omium.org>
CC: <srv_heupstream@...iatek.com>, <hui.liu@...iatek.com>,
<zhiyong.tao@...iatek.com>, <hsin-hsiung.wang@...iatek.com>,
<sean.wang@...iatek.com>, <macpaul.lin@...iatek.com>,
<yuchen.huang@...iatek.com>, <wen.su@...iatek.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-rtc@...r.kernel.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH 1/2] arm64: dts: mt8192: add PWRAP node
From: Hui Liu <hui.liu@...iatek.com>
Add pwrap node.
Signed-off-by: Hui Liu <hui.liu@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 53d790c335f9..9ef33dbf7a73 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -316,6 +316,18 @@ systimer: timer@...17000 {
clock-names = "clk13m";
};
+ pwrap: pwrap@...26000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@...20000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.25.1
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