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Message-ID: <6ee9419e-036d-586e-78e0-d3fc879642ab@intel.com>
Date: Thu, 27 Jan 2022 14:58:19 +0800
From: kernel test robot <yujie.liu@...el.com>
To: Hawking Zhang <Hawking.Zhang@....com>
CC: <kbuild-all@...ts.01.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Alex Deucher <alexander.deucher@....com>,
"Zhou, Peng Ju" <PengJu.Zhou@....com>,
Lijo Lazar <lijo.lazar@....com>
Subject: [agd5f:drm-next 124/190]
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:877:51: warning: Uninitialized
variable: reg_access_ctrl [uninitvar]
tree: https://gitlab.freedesktop.org/agd5f/linux.git drm-next
head: 63e583c8843f305a3e334a96d5de00435f4d38a2
commit: 5d447e296701484f3df5b31a7a078cbf1e3a9cc9 [124/190] drm/amdgpu: add helper for rlcg indirect reg access
compiler: riscv32-linux-gcc (GCC) 11.2.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <yujie.liu@...el.com>
cppcheck possible warnings: (new ones prefixed by >>, may not be real problems)
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:877:51: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:878:51: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:879:51: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:880:51: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:884:16: warning: Uninitialized struct member: reg_access_ctrl.grbm_cntl [uninitStructMember]
if (offset == reg_access_ctrl->grbm_cntl) {
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:888:23: warning: Uninitialized struct member: reg_access_ctrl.grbm_idx [uninitStructMember]
} else if (offset == reg_access_ctrl->grbm_idx) {
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:881:6: warning: Uninitialized struct member: reg_access_ctrl.spare_int [uninitStructMember]
if (reg_access_ctrl->spare_int)
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:882:49: warning: Uninitialized struct member: reg_access_ctrl.spare_int [uninitStructMember]
spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:901:7: warning: Uninitialized struct member: reg_access_ctrl.spare_int [uninitStructMember]
if (reg_access_ctrl->spare_int)
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:881:6: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
if (reg_access_ctrl->spare_int)
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:882:49: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:884:16: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
if (offset == reg_access_ctrl->grbm_cntl) {
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:888:23: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
} else if (offset == reg_access_ctrl->grbm_idx) {
^
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:901:7: warning: Uninitialized variable: reg_access_ctrl [uninitvar]
if (reg_access_ctrl->spare_int)
^
vim +877 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
5d447e29670148 Hawking Zhang 2022-01-18 858
5d447e29670148 Hawking Zhang 2022-01-18 859 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
5d447e29670148 Hawking Zhang 2022-01-18 860 {
5d447e29670148 Hawking Zhang 2022-01-18 @861 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
5d447e29670148 Hawking Zhang 2022-01-18 862 uint32_t timeout = 50000;
5d447e29670148 Hawking Zhang 2022-01-18 863 uint32_t i, tmp;
5d447e29670148 Hawking Zhang 2022-01-18 864 uint32_t ret = 0;
5d447e29670148 Hawking Zhang 2022-01-18 865 static void *scratch_reg0;
5d447e29670148 Hawking Zhang 2022-01-18 866 static void *scratch_reg1;
5d447e29670148 Hawking Zhang 2022-01-18 867 static void *scratch_reg2;
5d447e29670148 Hawking Zhang 2022-01-18 868 static void *scratch_reg3;
5d447e29670148 Hawking Zhang 2022-01-18 869 static void *spare_int;
5d447e29670148 Hawking Zhang 2022-01-18 870
5d447e29670148 Hawking Zhang 2022-01-18 871 if (!adev->gfx.rlc.rlcg_reg_access_supported) {
5d447e29670148 Hawking Zhang 2022-01-18 872 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 873 "indirect registers access through rlcg is not available\n");
5d447e29670148 Hawking Zhang 2022-01-18 874 return 0;
5d447e29670148 Hawking Zhang 2022-01-18 875 }
5d447e29670148 Hawking Zhang 2022-01-18 876
5d447e29670148 Hawking Zhang 2022-01-18 @877 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
5d447e29670148 Hawking Zhang 2022-01-18 @878 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
5d447e29670148 Hawking Zhang 2022-01-18 @879 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
5d447e29670148 Hawking Zhang 2022-01-18 @880 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
5d447e29670148 Hawking Zhang 2022-01-18 @881 if (reg_access_ctrl->spare_int)
5d447e29670148 Hawking Zhang 2022-01-18 882 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
5d447e29670148 Hawking Zhang 2022-01-18 883
5d447e29670148 Hawking Zhang 2022-01-18 @884 if (offset == reg_access_ctrl->grbm_cntl) {
5d447e29670148 Hawking Zhang 2022-01-18 885 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
5d447e29670148 Hawking Zhang 2022-01-18 886 writel(v, scratch_reg2);
5d447e29670148 Hawking Zhang 2022-01-18 887 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
5d447e29670148 Hawking Zhang 2022-01-18 @888 } else if (offset == reg_access_ctrl->grbm_idx) {
5d447e29670148 Hawking Zhang 2022-01-18 889 /* if the target reg offset is grbm_idx, write to scratch_reg3 */
5d447e29670148 Hawking Zhang 2022-01-18 890 writel(v, scratch_reg3);
5d447e29670148 Hawking Zhang 2022-01-18 891 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
5d447e29670148 Hawking Zhang 2022-01-18 892 } else {
5d447e29670148 Hawking Zhang 2022-01-18 893 /*
5d447e29670148 Hawking Zhang 2022-01-18 894 * SCRATCH_REG0 = read/write value
5d447e29670148 Hawking Zhang 2022-01-18 895 * SCRATCH_REG1[30:28] = command
5d447e29670148 Hawking Zhang 2022-01-18 896 * SCRATCH_REG1[19:0] = address in dword
5d447e29670148 Hawking Zhang 2022-01-18 897 * SCRATCH_REG1[26:24] = Error reporting
5d447e29670148 Hawking Zhang 2022-01-18 898 */
5d447e29670148 Hawking Zhang 2022-01-18 899 writel(v, scratch_reg0);
5d447e29670148 Hawking Zhang 2022-01-18 900 writel((offset | flag), scratch_reg1);
5d447e29670148 Hawking Zhang 2022-01-18 901 if (reg_access_ctrl->spare_int)
5d447e29670148 Hawking Zhang 2022-01-18 902 writel(1, spare_int);
5d447e29670148 Hawking Zhang 2022-01-18 903
5d447e29670148 Hawking Zhang 2022-01-18 904 for (i = 0; i < timeout; i++) {
5d447e29670148 Hawking Zhang 2022-01-18 905 tmp = readl(scratch_reg1);
5d447e29670148 Hawking Zhang 2022-01-18 906 if (!(tmp & flag))
5d447e29670148 Hawking Zhang 2022-01-18 907 break;
5d447e29670148 Hawking Zhang 2022-01-18 908 udelay(10);
5d447e29670148 Hawking Zhang 2022-01-18 909 }
5d447e29670148 Hawking Zhang 2022-01-18 910
5d447e29670148 Hawking Zhang 2022-01-18 911 if (i >= timeout) {
5d447e29670148 Hawking Zhang 2022-01-18 912 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
5d447e29670148 Hawking Zhang 2022-01-18 913 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
5d447e29670148 Hawking Zhang 2022-01-18 914 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 915 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
5d447e29670148 Hawking Zhang 2022-01-18 916 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
5d447e29670148 Hawking Zhang 2022-01-18 917 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 918 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
5d447e29670148 Hawking Zhang 2022-01-18 919 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
5d447e29670148 Hawking Zhang 2022-01-18 920 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 921 "regiser is not in range, rlcg failed to program reg: 0x%05x\n", offset);
5d447e29670148 Hawking Zhang 2022-01-18 922 } else {
5d447e29670148 Hawking Zhang 2022-01-18 923 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 924 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
5d447e29670148 Hawking Zhang 2022-01-18 925 }
5d447e29670148 Hawking Zhang 2022-01-18 926 } else {
5d447e29670148 Hawking Zhang 2022-01-18 927 dev_err(adev->dev,
5d447e29670148 Hawking Zhang 2022-01-18 928 "timeout: rlcg faled to program reg: 0x%05x\n", offset);
5d447e29670148 Hawking Zhang 2022-01-18 929 }
5d447e29670148 Hawking Zhang 2022-01-18 930 }
5d447e29670148 Hawking Zhang 2022-01-18 931 }
5d447e29670148 Hawking Zhang 2022-01-18 932
5d447e29670148 Hawking Zhang 2022-01-18 933 ret = readl(scratch_reg0);
5d447e29670148 Hawking Zhang 2022-01-18 934 return ret;
5d447e29670148 Hawking Zhang 2022-01-18 935 }
5d447e29670148 Hawking Zhang 2022-01-18 936
---
0-DAY CI Kernel Test Service, Intel Corporation
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