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Message-ID: <7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com>
Date: Fri, 28 Jan 2022 13:17:16 +0530
From: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
Vinod Koul <vkoul@...nel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Prasad <quic_psodagud@...cinc.com>,
Sai Prakash Ranjan <quic_saipraka@...cinc.com>
Subject: [PATCHv2 9/9] arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 10c25ad2d0c7..5a3d050b94f7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1102,6 +1102,13 @@ usb_1_dwc3: usb@...0000 {
phy-names = "usb2-phy", "usb3-phy";
};
};
+
+ system-cache-controller@...00000 {
+ compatible = "qcom,sm8450-llcc";
+ reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.33.1
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