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Message-ID: <CAAhSdy1VfWaSxPb0kLFtxz4acX6fBOuZ=7y7QRiGp0SydqD6ZA@mail.gmail.com>
Date: Fri, 28 Jan 2022 14:36:38 +0530
From: Anup Patel <anup@...infault.org>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Sagar Kadam <sagar.kadam@...ive.com>,
Rob Herring <robh+dt@...nel.org>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v4 2/2] dt-bindings: interrupt-controller: sifive,plic:
Group interrupt tuples
On Fri, Jan 28, 2022 at 2:34 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> To improve human readability and enable automatic validation, the tuples
> in "interrupts-extended" properties should be grouped using angle
> brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@...ux-m68k.org>
> Reviewed-by: Rob Herring <robh@...nel.org>
Looks good to me.
Reviewed-by: Anup Patel <anup@...infault.org>
Regards,
Anup
> ---
> v4:
> - No changes,
>
> v3:
> - Add Reviewed-by,
>
> v2:
> - Split in two patches.
> ---
> .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 57c06126c99502fa..0dfa6b26e09910a8 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -91,12 +91,11 @@ examples:
> #interrupt-cells = <1>;
> compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> interrupt-controller;
> - interrupts-extended = <
> - &cpu0_intc 11
> - &cpu1_intc 11 &cpu1_intc 9
> - &cpu2_intc 11 &cpu2_intc 9
> - &cpu3_intc 11 &cpu3_intc 9
> - &cpu4_intc 11 &cpu4_intc 9>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> reg = <0xc000000 0x4000000>;
> riscv,ndev = <10>;
> };
> --
> 2.25.1
>
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