[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <YfZskTVEDx8AAtYh@zn.tnic>
Date: Sun, 30 Jan 2022 11:46:41 +0100
From: Borislav Petkov <bp@...e.de>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: x86-ml <x86@...nel.org>, lkml <linux-kernel@...r.kernel.org>
Subject: [GIT PULL] x86/urgent for v5.17-rc2
Hi Linus,
please pull x86/urgent for 5.17.
Thx.
---
The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07:
Linux 5.17-rc1 (2022-01-23 10:12:53 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tags/x86_urgent_for_v5.17_rc2
for you to fetch changes up to e464121f2d40eabc7d11823fb26db807ce945df4:
x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN (2022-01-25 18:40:30 +0100)
----------------------------------------------------------------
- Add another Intel CPU model to the list of CPUs supporting the
processor inventory unique number
- Allow writing to MCE thresholding sysfs files again - a previous
change had accidentally disabled it and no one noticed. Goes to show how
much is this stuff used
----------------------------------------------------------------
Tony Luck (1):
x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
Yazen Ghannam (1):
x86/MCE/AMD: Allow thresholding interface updates after init
arch/x86/kernel/cpu/mce/amd.c | 2 +-
arch/x86/kernel/cpu/mce/intel.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--
Regards/Gruss,
Boris.
SUSE Software Solutions Germany GmbH, GF: Ivo Totev, HRB 36809, AG Nürnberg
Powered by blists - more mailing lists