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Date: Mon, 31 Jan 2022 11:47:23 +0000
From: <conor.dooley@...rochip.com>
To: <linus.walleij@...aro.org>, <brgl@...ev.pl>, <robh+dt@...nel.org>,
<jassisinghbrar@...il.com>, <thierry.reding@...il.com>,
<u.kleine-koenig@...gutronix.de>, <lee.jones@...aro.org>,
<a.zummo@...ertech.it>, <alexandre.belloni@...tlin.com>,
<paul.walmsley@...ive.com>, <palmer@...belt.com>,
<aou@...s.berkeley.edu>, <geert@...ux-m68k.org>,
<linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-i2c@...r.kernel.org>,
<linux-pwm@...r.kernel.org>, <linux-rtc@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>
CC: <krzysztof.kozlowski@...onical.com>, <bin.meng@...driver.com>,
<heiko@...ech.de>, <lewis.hanly@...rochip.com>,
<conor.dooley@...rochip.com>, <daire.mcnamara@...rochip.com>,
<ivan.griffin@...rochip.com>, <atishp@...osinc.com>
Subject: [PATCH v5 08/12] riscv: dts: microchip: add fpga fabric section to icicle kit
From: Conor Dooley <conor.dooley@...rochip.com>
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++
.../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 1 +
3 files changed, 34 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..c1dcd56b0679
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ core_pwm0: pwm@...00000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41000000 0x0 0xF0>;
+ microchip,sync-update = /bits/ 16 <0>;
+ #pwm-cells = <2>;
+ clocks = <&clkcfg CLK_FIC3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@...00000 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ interrupt-parent = <&plic>;
+ interrupts = <122>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 6d19ba196f12..ab803f71626a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -68,6 +68,10 @@ &mmc {
sd-uhs-sdr104;
};
+&i2c2 {
+ status = "okay";
+};
+
&emac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
@@ -86,3 +90,7 @@ phy1: ethernet-phy@9 {
ti,fifo-depth = <0x01>;
};
};
+
+&core_pwm0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 717e39b30a15..c7d73756c9b8 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -3,6 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.35.0
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