linux-kernel - [irqchip: irq/irqchip-fixes] dt-bindings: update riscv plic compatible string

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Date:   Wed, 02 Feb 2022 10:53:12 -0000
From:   "irqchip-bot for Guo Ren" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Guo Ren <guoren@...ux.alibaba.com>,
        Anup Patel <anup@...infault.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Rob Herring <robh@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Samuel Holland <samuel@...lland.org>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-fixes] dt-bindings: update riscv plic compatible string

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     321a8be37e1a93cefeae990107533142c8515933
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/321a8be37e1a93cefeae990107533142c8515933
Author:        Guo Ren <guoren@...ux.alibaba.com>
AuthorDate:    Sun, 30 Jan 2022 21:56:33 +08:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Wed, 02 Feb 2022 10:48:50 

dt-bindings: update riscv plic compatible string

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Cc: Anup Patel <anup@...infault.org>
Cc: Heiko Stuebner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Palmer Dabbelt <palmer@...belt.com>
Cc: Samuel Holland <samuel@...lland.org>
Reviewed-by: Rob Herring <robh@...nel.org>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20220130135634.1213301-2-guoren@kernel.org
---
 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 0dfa6b2..27092c6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
+  T-HEAD PLIC implementation requires setting a delegation bit to allow access
+  from S-mode. So add thead,c900-plic to distinguish them.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@...ive.com>
   - Paul Walmsley  <paul.walmsley@...ive.com>
@@ -42,12 +46,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,fu540-c000-plic
-          - starfive,jh7100-plic
-          - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu540-c000-plic
+              - starfive,jh7100-plic
+              - canaan,k210-plic
+          - const: sifive,plic-1.0.0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-plic
+          - const: thead,c900-plic
 
   reg:
     maxItems: 1