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Date: Thu, 3 Feb 2022 16:34:08 -0500
From: Adrien Thierry <athierry@...hat.com>
To: linux-serial@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Adrien Thierry <athierry@...hat.com>,
Jeremy Linton <jeremy.linton@....com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Florian Fainelli <f.fainelli@...il.com>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
bcm-kernel-feedback-list@...adcom.com
Subject: [PATCH v2] serial: 8250_bcm2835aux: Add ACPI support
Add ACPI support to 8250_bcm2835aux driver. This makes it possible to
use the miniuart on the Raspberry Pi with the tianocore/edk2 UEFI
firmware.
Signed-off-by: Adrien Thierry <athierry@...hat.com>
---
V1 -> V2: Refactored code to remove unnecessary conditional paths and
intermediate variables
drivers/tty/serial/8250/8250_bcm2835aux.c | 87 ++++++++++++++++++-----
1 file changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c b/drivers/tty/serial/8250/8250_bcm2835aux.c
index fd95860cd661..b7cec2a3b5f7 100644
--- a/drivers/tty/serial/8250/8250_bcm2835aux.c
+++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
@@ -12,6 +12,7 @@
* simultaneously to rs485.
*/
+#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -44,6 +45,10 @@ struct bcm2835aux_data {
u32 cntl;
};
+struct bcm2835_aux_serial_acpi_driver_data {
+ resource_size_t offset;
+};
+
static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up)
{
if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
@@ -82,8 +87,11 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
{
struct uart_8250_port up = { };
struct bcm2835aux_data *data;
+ struct bcm2835_aux_serial_acpi_driver_data *acpi_data;
struct resource *res;
int ret;
+ resource_size_t offset = 0;
+ unsigned int uartclk;
/* allocate the custom structure */
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
@@ -110,8 +118,11 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
/* get the clock - this also enables the HW */
data->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(data->clk))
- return dev_err_probe(&pdev->dev, PTR_ERR(data->clk), "could not get clk\n");
+ if (IS_ERR(data->clk)) {
+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "could not get clk\n");
+ }
/* get the interrupt */
ret = platform_get_irq(pdev, 0);
@@ -125,20 +136,47 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "memory resource not found");
return -EINVAL;
}
- up.port.mapbase = res->start;
- up.port.mapsize = resource_size(res);
-
- /* Check for a fixed line number */
- ret = of_alias_get_id(pdev->dev.of_node, "serial");
- if (ret >= 0)
- up.port.line = ret;
-
- /* enable the clock as a last step */
- ret = clk_prepare_enable(data->clk);
- if (ret) {
- dev_err(&pdev->dev, "unable to enable uart clock - %d\n",
- ret);
- return ret;
+
+ if (has_acpi_companion(&pdev->dev)) {
+ const struct acpi_device_id *match;
+
+ match = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
+ acpi_data = (struct bcm2835_aux_serial_acpi_driver_data *)match->driver_data;
+
+ /* Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi)
+ * describe the miniuart with a base address that encompasses the auxiliary
+ * registers shared between the miniuart and spi.
+ *
+ * This is due to historical reasons, see discussion here :
+ * https://edk2.groups.io/g/devel/topic/87501357#84349
+ *
+ * We need to add the offset between the miniuart and auxiliary
+ * registers to get the real miniuart base address.
+ */
+ offset = acpi_data->offset;
+ }
+
+ up.port.mapbase = res->start + offset;
+ up.port.mapsize = resource_size(res) - offset;
+
+ if (dev_of_node(&pdev->dev)) {
+ /* Check for a fixed line number */
+ ret = of_alias_get_id(pdev->dev.of_node, "serial");
+ if (ret >= 0)
+ up.port.line = ret;
+
+ /* enable the clock as a last step */
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to enable uart clock - %d\n",
+ ret);
+ return ret;
+ }
+
+ uartclk = clk_get_rate(data->clk);
}
/* the HW-clock divider for bcm2835aux is 8,
@@ -146,7 +184,7 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
* so we have to multiply the actual clock by 2
* to get identical baudrates.
*/
- up.port.uartclk = clk_get_rate(data->clk) * 2;
+ up.port.uartclk = uartclk * 2;
/* register the port */
ret = serial8250_register_8250_port(&up);
@@ -159,7 +197,9 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
return 0;
dis_clk:
- clk_disable_unprepare(data->clk);
+ if (dev_of_node(&pdev->dev))
+ clk_disable_unprepare(data->clk);
+
return ret;
}
@@ -173,16 +213,27 @@ static int bcm2835aux_serial_remove(struct platform_device *pdev)
return 0;
}
+static const struct bcm2835_aux_serial_acpi_driver_data bcm2835_acpi_data = {
+ .offset = 0x40
+};
+
static const struct of_device_id bcm2835aux_serial_match[] = {
{ .compatible = "brcm,bcm2835-aux-uart" },
{ },
};
MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match);
+static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = {
+ { "BCM2836", (kernel_ulong_t)&bcm2835_acpi_data },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match);
+
static struct platform_driver bcm2835aux_serial_driver = {
.driver = {
.name = "bcm2835-aux-uart",
.of_match_table = bcm2835aux_serial_match,
+ .acpi_match_table = bcm2835aux_serial_acpi_match,
},
.probe = bcm2835aux_serial_probe,
.remove = bcm2835aux_serial_remove,
base-commit: 1f2cfdd349b7647f438c1e552dc1b983da86d830
--
2.34.1
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