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Message-Id: <20220203120604.128396-11-james.clark@arm.com>
Date: Thu, 3 Feb 2022 12:05:58 +0000
From: James Clark <james.clark@....com>
To: suzuki.poulose@....com, mathieu.poirier@...aro.org,
coresight@...ts.linaro.org
Cc: leo.yan@...aro.com, mike.leach@...aro.org,
James Clark <james.clark@....com>,
Leo Yan <leo.yan@...aro.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 10/15] coresight: Make ETM3x ETMTECR1 register accesses consistent with sysreg.h
This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.
Signed-off-by: James Clark <james.clark@....com>
---
drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +-
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index cf64ce73a741..35e4bdee848c 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config)
* set all bits in register 0x007, the ETMTECR2, to 0
* set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
*/
- config->enable_ctrl1 = BIT(24);
+ config->enable_ctrl1 = ETMTECR1_INC_EXC;
config->enable_ctrl2 = 0x0;
config->enable_event = ETM_HARD_WIRE_RES_A;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index e8c7649f123e..68fcbf4ce7a8 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -474,7 +474,7 @@ static ssize_t addr_start_store(struct device *dev,
config->addr_val[idx] = val;
config->addr_type[idx] = ETM_ADDR_TYPE_START;
config->startstop_ctrl |= (1 << idx);
- config->enable_ctrl1 |= BIT(25);
+ config->enable_ctrl1 |= ETMTECR1_START_STOP;
spin_unlock(&drvdata->spinlock);
return size;
--
2.28.0
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