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Message-ID: <13dc6f72-8ef4-6990-1c67-2b92c6894e87@oss.nxp.com>
Date:   Thu, 3 Feb 2022 17:38:10 +0100
From:   Yannick Vignon <yannick.vignon@....nxp.com>
To:     "Russell King (Oracle)" <linux@...linux.org.uk>
Cc:     Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Rayagond Kokatanur <rayagond@...avyalabs.com>,
        netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        sebastien.laveze@....nxp.com, Vladimir Oltean <olteanv@...il.com>,
        Xiaoliang Yang <xiaoliang.yang_1@....com>, mingkai.hu@....com,
        Joakim Zhang <qiangqing.zhang@....com>,
        Yannick Vignon <yannick.vignon@....com>
Subject: Re: [PATCH net] net: stmmac: ensure PTP time register reads are
 consistent

On 2/3/2022 5:28 PM, Russell King (Oracle) wrote:
> On Thu, Feb 03, 2022 at 05:00:25PM +0100, Yannick Vignon wrote:
>> From: Yannick Vignon <yannick.vignon@....com>
>>
>> Even if protected from preemption and interrupts, a small time window
>> remains when the 2 register reads could return inconsistent values,
>> each time the "seconds" register changes. This could lead to an about
>> 1-second error in the reported time.
> 
> Have you checked whether the hardware protects against this (i.o.w. the
> hardware latches the PTP_STSR value when PTP_STNSR is read, or vice
> versa? Several PTP devices I've looked at do this to allow consistent
> reading.
> 

It doesn't. I was able to observe inconsistent values doing reads in 
either order, and we had already observed the issue with that same IP on 
another device (Cortex-M based, not running Linux). It's not easy to 
reproduce, the time window is small, but it's there.

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