Message-ID: <06f84f27-973d-1dae-e2c3-3fda4e368331@gmail.com>
Date:   Thu, 3 Feb 2022 11:33:26 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Sudeep Holla <sudeep.holla@....com>
Cc:     linux-arm-kernel@...ts.infradead.org,
        "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <bcm-kernel-feedback-list@...adcom.com>,
        Mark Rutland <mark.rutland@....com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/4] Broadcom STB PM PSCI extensions



On 2/3/2022 10:52 AM, Sudeep Holla wrote:
> Correction: it is known as "freeze" rather than "idle" in terms of values
> as per /sys/power/state. Sorry for referring it as "idle" and creating any
> confusion.
> 
> On Thu, Feb 03, 2022 at 09:36:28AM -0800, Florian Fainelli wrote:
>>
>>
>> On 2/3/2022 3:14 AM, Sudeep Holla wrote:
>>> On Fri, Jan 21, 2022 at 07:54:17PM -0800, Florian Fainelli wrote:
>>>> Hi all,
>>>>
>>>> This patch series contains the Broadcom STB PSCI extensions which adds
>>>> some additional functions on top of the existing standard PSCI interface
>>>> which is the reason for having the driver implement a custom
>>>> suspend_ops.
>>>>
>>>> These platforms have traditionally supported a mode that is akin to
>>>> ACPI's S2 with the CPU in WFI and all of the chip being clock gated
>>>> which is entered with "echo standby > /sys/power/state". Additional a
>>>> true suspend to DRAM as defined in ACPI by S3 is implemented with "echo
>>>> mem > /sys/power/state".
>>>
>>> How different is the above "standby" state compare to the standard "idle"
>>> (a.k.a suspend-to-idle which is different from system-to-ram/S3) ?
>>
>> There are a few differences:
>>
>> - s2idle does not power gate the secondary CPUs
>>
> 
> Not sure what you mean by that ? S2I takes CPUs to deepest idle state.
> If you want shallower states, one possible option is the disable deeper
> states from the userspace.

What I mean is that we do not get to call PSCI CPU_OFF here so the CPUs 
are idle, but not power gated. Those CPUs do not have any other idle 
state other than WFI because the HW designers sort of forgot or rather 
did not know that wiring up the ARM GIC power controller back to the 
power gating logic of the CPU was a good idea.

> 
>> - s2idle requires the use of in-band interrupts for wake-up
>>
> 
> I am not sure if that is true. S2I behaves very similar to S2R except it
> has low wake latency as all secondaries CPUs are not hotplugged out.

OK, the fact that secondary CPUs are not hot-plugged could be remedied 
by doing this ahead of entering s2idle by user-space so this is not a 
valid argument from me anymore.

> 
>> The reasons for implementing "standby" are largely two fold:
>>
>> - we need to achieve decent power savings (typically below 0.5W for the
>> whole system while allowing Wake-on-WLAN, GPIO, RTC, infrared, etc.)
>>
> 
> I fail to understand how that is a problem from S2I. It is probably worth
> checking if there are any unnecessary IRQF_NO_SUSPEND users. Check section
> IRQF_NO_SUSPEND and enable_irq_wake() in [1]. I don't see any issues other
> wise in terms of unnecessary/spurious wakeup by in-band(to be precise
> no-wake up) interrupts.

I don't think your hyperlink referenced by [1] was provided, but my 
quick testing with:

echo s2idle > /sys/power/mem_sleep
echo mem > /sys/power/state

appears to work to some extent when I use peripherals that can generate 
in-band interrupts.

It looks like we have s2idle_ops that allows a platform to override some 
of the operations before/after entering s2idle, however the actual 
s2idle idle loop is still within the kernel, so we will not call into 
the ARM Trusted Firmware and engage the power management state machine.

This means that there will not be any of the clock gating that only the 
hardware state machine is capable of performing, the DRAM controller as 
a result will not enter self refresh power down, and in addition the 
side band wake-up interrupts will not be activate because the interrupt 
controller that aggregates them only outputs to the ARM GIC when the 
state machine has been engaged.

Essentially, what we need for our systems is a controlled system entry 
with semantics similar if not identical to that of S2R but with a 
shallower state that does not cut the power to 90% of the SoC (unlike 
S2R) such that we have a quicker suspend and resume latency. Years ago 
when we only had MIPS-based and 32-bit ARM SoCs, we did come up with 
using "standby" (see drivers/soc/bcm/brcmstb/pm/*) and we naturally 
mapped that when we switched over to ARMv8 capable devices.

> 
>> - we have a security subsystem that requires the CPUs to be either power
>> gated or idle in order the hardware state machine that lets the system enter
>> such a state and allows the out of band interrupts from being wake-up
>> sources
>>
> 
> It should work unless I have completely misunderstood how S2I works.
> 
>>> Suspend to idle takes all the CPUs to lowest possible power state instead
>>> of cpu-hotplug in S2R. Also I assume some userspace has to identify when
>>> to enter "standby" vs "mem" right ? I am trying to see how addition of
>>> "idle" changes that(if it does). Sorry for too many questions.
>>>
>>
>> Right that user-space in our case is either custom (like RDK, or completely
>> custom), or is Android. For Android it looks like we are carrying a patch
>> that makes "mem" de-generate into "standby" but this is largely because we
>> had historically problems with "mem" that are being addressed (completely
>> orthogonal).
>>
> 
> Thanks for the info.
> 
>> I did not consider it as a viable option at the time, but if we were to
>> implement "standby" in drivers/firmware/psci/psci.c would that be somewhat
>> acceptable?
>>
> 
> We have been pointing anyone needing standby so far to S2I and so far no one
> has shouted that it doesn't suffice. Let me know what is missing.
> 

-- 
Florian

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