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Message-Id: <1643948739-14889-2-git-send-email-hayashi.kunihiko@socionext.com>
Date: Fri, 4 Feb 2022 13:25:37 +0900
From: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Masami Hiramatsu <mhiramat@...nel.org>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
Subject: [PATCH v2 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible
string, clock and reset lines for the SoC to the document.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
---
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index 179ab0858482..437e61618d06 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -20,7 +20,9 @@ allOf:
properties:
compatible:
- const: socionext,uniphier-pro5-pcie-ep
+ enum:
+ - socionext,uniphier-pro5-pcie-ep
+ - socionext,uniphier-nx1-pcie-ep
reg:
minItems: 4
@@ -41,20 +43,26 @@ properties:
- const: atu
clocks:
+ minItems: 1
maxItems: 2
clock-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
resets:
+ minItems: 1
maxItems: 2
reset-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
num-ib-windows:
const: 16
--
2.7.4
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