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Message-Id: <20220204073940.1258263-1-eranian@google.com>
Date:   Thu,  3 Feb 2022 23:39:40 -0800
From:   Stephane Eranian <eranian@...gle.com>
To:     linux-kernel@...r.kernel.org
Cc:     peterz@...radead.org, will@...nel.org, ashoks@...adcom.com,
        mark.rutland@....com
Subject: [PATCH] perf/arm64: fix mapping for HW_BRANCH_INSTRUCTIONS on PMUv3

With the existing code, the following command:

$ perf stat -e branches sleep 0
 Performance counter stats for 'sleep 0':
   <not supported>      branches

on N1 core (pmuv3).

This is due to the fact that the mapping for the generic event is wrong.
It is using ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED which is not implemented
on N1 (and most likely on any PMUv3 implementations). However, there is
another supported event ARMV8_PMUV3_PERFCTR_BR_RETIRED measuring the same
condition.

This patch switches the mapping to ARMV8_PMUV3_PERFCTR_BR_RETIRED so that
the perf stat command above works.

Signed-off-by: Stephane Eranian <eranian@...gle.com>
---
 arch/arm64/kernel/perf_event.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index cab678ed6618..ec2b98343a0b 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -45,7 +45,7 @@ static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
-	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV8_PMUV3_PERFCTR_BR_RETIRED,
 	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 	[PERF_COUNT_HW_BUS_CYCLES]		= ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
-- 
2.35.0.263.gb82422642f-goog

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