linux-kernel - Re: [PATCH v7 3/4] phy: rockchip: add naneng combo phy for RK3568

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Date:   Fri, 4 Feb 2022 13:17:02 +0100
From:   Johan Jonker <jbx6244@...il.com>
To:     Yifeng Zhao <yifeng.zhao@...k-chips.com>, heiko@...ech.de
Cc:     robh+dt@...nel.org, devicetree@...r.kernel.org, vkoul@...nel.org,
        michael.riesch@...fvision.net, linux-rockchip@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-phy@...ts.infradead.org, kishon@...com,
        p.zabel@...gutronix.de, cl@...k-chips.com,
        kever.yang@...k-chips.com, lee.jones@...aro.org,
        wulf@...k-chips.com, Frank Wunderlich <frank-w@...lic-files.de>
Subject: Re: [PATCH v7 3/4] phy: rockchip: add naneng combo phy for RK3568

Hi Heiko, Frank and others,

China is on new year vacation.

Question for Heiko:
With xpcs in a separate node, how do we pass phy modes from gmac to
xpcs, multiphy in a correct DT way?
Can we brand xpcs as phy?
Please advise.

Johan
===

Found example for the way Rockchip connects sgmii in the manufacturer DT.
https://github.com/Poco-Ye/rk-ethernet/blob/master/SGMII.rar

>From gmac1.txt:

> &mdio1 {
>         sgmii_phy: phy@1 {
         sgmii_phy: phy@0 { // ???

What is correct?

>                 compatible = "ethernet-phy-ieee802.3-c22";
>                 reg = <0x0>;

C45E
Clause 45 PHY Enable
When this bit is set, Clause 45 capable PHY is connected to MDIO.
When this bit is reset, Clause 22 capable PHY is connected to
MDIO.
Values:
1'b0: Clause 45 PHY is disabled
1'b1: Clause 45 PHY is enabled

>         };
> };
>
>
> &combphy2_psq {
> +       rockchip,sgmii-mac-sel = <1>;
>         status = "okay";
> };
>
>
> &gmac0 {
> 	phy-mode = "sgmii";
> 	
> 	rockchip,pipegrf = <&pipegrf>;
> 	rockchip,xpcs = <&xpcs>;
>
> 	snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
> 	snps,reset-active-low;
> 	/* Reset time is 20ms, 100ms for rtl8211f */
> 	snps,reset-delays-us = <0 20000 100000>;
>
> 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
> 	assigned-clock-parents = <&gmac1_xpcsclk>;
>
> +	pinctrl-0 = <&gmac1m0_miim>;
> 	power-domains = <&power RK3568_PD_PIPE>;
> 	phys = <&combphy2_psq PHY_TYPE_SGMII>;
> +	phy-handle = <&sgmii_phy>;
>
> 	status = "okay";
> };

===

Proposal:
xpcs driver passes mode info to multiphy driver.
Phy arg is used for gmac source selection for PHY_INTERFACE_MODE_SGMII
and PHY_INTERFACE_MODE_QSGMII.

> 	phys = <&xpcs 0>;

===

{
	gmac0_xpcsclk: xpcs-gmac0-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "clk_gmac0_xpcs_mii";
		#clock-cells = <0>;
	};

	gmac1_xpcsclk: xpcs-gmac1-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "clk_gmac1_xpcs_mii";
		#clock-cells = <0>;
	};

	xpcs: syscon@...00000 {
		compatible = "rockchip,rk3568-xpcs", "syscon";
		reg = <0x0 0xfda00000 0x0 0x200000>;
		clocks = <&cru PCLK_XPCS>;
		clock-names = "pclk_xpcs";

>		phys = <&multiphy2>;

		power-domains = <&power RK3568_PD_PIPE>;
 		rockchip,pipegrf = <&pipegrf>; // Switch between gmac0 and gmac1
		status = "disabled";
	};
}

&mdio1 {
         sgmii_phy: phy@0 {
                 compatible = "ethernet-phy-ieee802.3-c22";
                 reg = <0x0>;
         };
 };


&multiphy2 {
         status = "okay";
};


&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
 	assigned-clock-parents = <&gmac1_xpcsclk>;

 	phys = <&combphy2_psq PHY_TYPE_SGMII>;
	phy-handle = <&sgmii_phy>;
 	phy-mode = "sgmii";

> 	phys = <&xpcs 0>;

	pinctrl-0 = <&gmac1m0_miim>;

 	snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
 	/* Reset time is 20ms, 100ms for rtl8211f */
 	snps,reset-delays-us = <0 20000 100000>;

	status = "okay";
};

On 1/3/22 19:26, Johan Jonker wrote:
> Hi Yifeng, Kishon, rob+dt,
> 
> Some comments, have a look if it's useful.
> 
> ====
> 
> Could the DT and phy maintainer advise the correct/right driver
> structure to Yifeng, so that we can move forward!
> 
> ====
>