linux-kernel - [PATCH] PCI: fu740: RFC: force gen1 and get devices probing

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Message-Id: <20220204183316.328937-1-ben.dooks@codethink.co.uk>
Date:   Fri,  4 Feb 2022 18:33:16 +0000
From:   Ben Dooks <ben.dooks@...ethink.co.uk>
To:     paul.walmsley@...ive.com, greentime.hu@...ive.com
Cc:     lorenzo.pieralisi@....com, robh@...nel.org, kw@...ux.com,
        bhelgaas@...gle.com, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        Ben Dooks <ben.dooks@...ethink.co.uk>
Subject: [PATCH] PCI: fu740: RFC: force gen1 and get devices probing

The dw pcie core does not probe devices unless this fix
from u-boot is applied. The link must be changed to gen1
and then the system will see all the other pcie devices
behind the unmatched board's bridge.

This is a quick PoC to try and get our test farm working
when a system does not have the pcie initialised by a
u-boot script.

I will look at a proper patch when I am back in the office
---
 drivers/pci/controller/dwc/pcie-fu740.c | 37 +++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c
index 960e58ead5f2..44f792764e45 100644
--- a/drivers/pci/controller/dwc/pcie-fu740.c
+++ b/drivers/pci/controller/dwc/pcie-fu740.c
@@ -181,11 +181,48 @@ static void fu740_pcie_init_phy(struct fu740_pcie *afp)
 	fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
 }
 
+/* u-boot forces system to gen1 otherwise nothing probes... */
+static void pcie_sifive_force_gen1(struct dw_pcie *dw, struct fu740_pcie *afp )
+{
+	unsigned val;
+
+#if 0
+	/* u-boot code */
+        /* ctrl_ro_wr_enable */
+        val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+        val |= DBI_RO_WR_EN;
+        writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+
+        /* configure link cap */
+        linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
+        linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK;
+        writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
+
+        /* ctrl_ro_wr_disable */
+        val &= ~DBI_RO_WR_EN;
+        writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+#endif
+
+	val = readl_relaxed(dw->dbi_base +  PCIE_MISC_CONTROL_1_OFF);
+	val |= PCIE_DBI_RO_WR_EN;
+	writel_relaxed(val, dw->dbi_base +  PCIE_MISC_CONTROL_1_OFF);
+
+	val = readl(dw->dbi_base + 0x70 + 0x0c);
+	val |= 0xf;
+	writel(val, dw->dbi_base + 0x70 + 0x0c);
+
+	val = readl_relaxed(dw->dbi_base +  PCIE_MISC_CONTROL_1_OFF);
+	val &= ~PCIE_DBI_RO_WR_EN;
+	writel_relaxed(val, dw->dbi_base +  PCIE_MISC_CONTROL_1_OFF);
+}
+
 static int fu740_pcie_start_link(struct dw_pcie *pci)
 {
 	struct device *dev = pci->dev;
 	struct fu740_pcie *afp = dev_get_drvdata(dev);
 
+	pcie_sifive_force_gen1(pci, afp);
+
 	/* Enable LTSSM */
 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
 	return 0;
-- 
2.34.1