linux-kernel - Re: [PATCH] crypto: octeontx2: increase CPT HW instruction queue length

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Sat, 5 Feb 2022 15:30:42 +1100
From:   Herbert Xu <herbert@...dor.apana.org.au>
To:     Shijith Thotton <sthotton@...vell.com>
Cc:     Arnaud Ebalard <arno@...isbad.org>,
        Boris Brezillon <bbrezillon@...nel.org>,
        Srujana Challa <schalla@...vell.com>,
        linux-crypto@...r.kernel.org, jerinj@...vell.com,
        sgoutham@...vell.com, "David S. Miller" <davem@...emloft.net>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] crypto: octeontx2: increase CPT HW instruction queue
 length

On Tue, Jan 25, 2022 at 11:56:24PM +0530, Shijith Thotton wrote:
> From: Srujana Challa <schalla@...vell.com>
> 
> LDWB is getting incorrectly used in HW when
> CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
> 320 free entries. So, increase HW instruction queue size by 320 and give
> 320 entries less for SW/NIX RX as a SW workaround.
> 
> Signed-off-by: Srujana Challa <schalla@...vell.com>
> Signed-off-by: Shijith Thotton <sthotton@...vell.com>
> ---
>  drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt