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Message-Id: <20220205060919.88656-1-pbonzini@redhat.com>
Date: Sat, 5 Feb 2022 01:09:19 -0500
From: Paolo Bonzini <pbonzini@...hat.com>
To: torvalds@...ux-foundation.org
Cc: linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: [GIT PULL] KVM fixes for Linux 5.17-rc3
Linus,
The following changes since commit 26291c54e111ff6ba87a164d85d4a4e134b7315c:
Linux 5.17-rc2 (2022-01-30 15:37:07 +0200)
are available in the Git repository at:
https://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to 7e6a6b400db8048bd1c06e497e338388413cf5bc:
Merge tag 'kvmarm-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD (2022-02-05 00:58:25 -0500)
----------------------------------------------------------------
ARM:
* A couple of fixes when handling an exception while a SError has been delivered
* Workaround for Cortex-A510's single-step erratum
RISCV:
* Make CY, TM, and IR counters accessible in VU mode
* Fix SBI implementation version
x86:
* Report deprecation of x87 features in supported CPUID
* Preparation for fixing an interrupt delivery race on AMD hardware
* Sparse fix
All except POWER and s390:
* Rework guest entry code to correctly mark noinstr areas and fix vtime'
accounting (for x86, this was already mostly correct but not entirely;
for ARM, MIPS and RISC-V it wasn't)
----------------------------------------------------------------
Anup Patel (1):
RISC-V: KVM: Fix SBI implementation version
James Morse (3):
KVM: arm64: Avoid consuming a stale esr value when SError occur
KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs
KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata
Janosch Frank (1):
kvm: Move KVM_GET_XSAVE2 IOCTL definition at the end of kvm.h
Jim Mattson (1):
KVM: x86: Report deprecated x87 features in supported CPUID
Mark Rutland (5):
kvm: add guest_state_{enter,exit}_irqoff()
kvm/mips: rework guest entry logic
kvm/x86: rework guest entry logic
kvm/arm64: rework guest entry logic
kvm/riscv: rework guest entry logic
Mayuresh Chitale (1):
RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
Paolo Bonzini (2):
Merge tag 'kvm-riscv-fixes-5.17-1' of https://github.com/kvm-riscv/linux into HEAD
Merge tag 'kvmarm-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
Sean Christopherson (2):
KVM: x86: Move delivery of non-APICv interrupt into vendor code
KVM: x86: Use ERR_PTR_USR() to return -EFAULT as a __user pointer
Documentation/arm64/silicon-errata.rst | 2 +
arch/arm64/Kconfig | 16 +++++
arch/arm64/kernel/cpu_errata.c | 8 +++
arch/arm64/kvm/arm.c | 51 ++++++++++-----
arch/arm64/kvm/handle_exit.c | 8 +++
arch/arm64/kvm/hyp/include/hyp/switch.h | 23 ++++++-
arch/arm64/tools/cpucaps | 5 +-
arch/mips/kvm/mips.c | 50 ++++++++++++--
arch/riscv/kvm/vcpu.c | 48 +++++++++-----
arch/riscv/kvm/vcpu_sbi_base.c | 3 +-
arch/x86/include/asm/kvm-x86-ops.h | 2 +-
arch/x86/include/asm/kvm_host.h | 3 +-
arch/x86/kvm/cpuid.c | 13 ++--
arch/x86/kvm/lapic.c | 10 +--
arch/x86/kvm/svm/svm.c | 21 +++++-
arch/x86/kvm/vmx/vmx.c | 21 +++++-
arch/x86/kvm/x86.c | 10 +--
arch/x86/kvm/x86.h | 45 -------------
include/linux/kvm_host.h | 112 +++++++++++++++++++++++++++++++-
include/uapi/linux/kvm.h | 6 +-
20 files changed, 336 insertions(+), 121 deletions(-)
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