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Message-ID: <20220205162144.30240-3-vidyas@nvidia.com>
Date: Sat, 5 Feb 2022 21:51:36 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <bhelgaas@...gle.com>, <lorenzo.pieralisi@....com>,
<robh+dt@...nel.org>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>
CC: <kishon@...com>, <vkoul@...nel.org>, <kw@...ux.com>,
<krzysztof.kozlowski@...onical.com>, <p.zabel@...gutronix.de>,
<mperttunen@...dia.com>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
<sagar.tv@...il.com>
Subject: [PATCH V1 02/10] dt-bindings: power: Add Tegra234 PCIe power domains
Add power domain IDs for the four PCIe power partitions found on
Tegra234.
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
.../dt-bindings/power/tegra234-powergate.h | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 include/dt-bindings/power/tegra234-powergate.h
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
new file mode 100644
index 000000000000..e989f84b24f6
--- /dev/null
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
+#define __ABI_MACH_T234_POWERGATE_T234_H_
+
+#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U
+#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U
+#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U
+#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U
+#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U
+#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U
+#define TEGRA234_POWER_DOMAIN_MGBEA 17U
+#define TEGRA234_POWER_DOMAIN_MGBEB 18U
+#define TEGRA234_POWER_DOMAIN_MGBEC 19U
+
+#endif
--
2.17.1
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