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Date: Sun, 6 Feb 2022 14:58:03 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Rob Herring <robh+dt@...nel.org>,
Lukasz Luba <lukasz.luba@....com>,
Alim Akhtar <alim.akhtar@...sung.com>,
Dmitry Osipenko <digetx@...il.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-pm@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v3 4/8] dt-bindings: memory: lpddr3: adjust IO width to spec
According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register
Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only
16- and 32-bit IO width. Drop the unsupported others.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
---
.../bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
index e36f3607e25a..d6787b5190ee 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
@@ -34,10 +34,8 @@ properties:
description: |
IO bus width in bits of SDRAM chip.
enum:
- - 64
- 32
- 16
- - 8
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
--
2.32.0
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