[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220206144343.2194-1-crawford.benjamin15@gmail.com>
Date: Sun, 6 Feb 2022 14:43:43 +0000
From: Benjamin Mordaunt <crawford.benjamin15@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Neil Armstrong <narmstrong@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: Benjamin Mordaunt <crawford.benjamin15@...il.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2] add pmu to amlogic meson sm1
---
The dts for meson sm1 appears to omit the SoC's PMU,
which is essential for accessing perf events regarding
e.g. cache on e.g. the Odroid C4 platform. Add it.
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 3d8b1f4f2..4147eecd2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -6,6 +6,8 @@
#include "meson-g12-common.dtsi"
#include <dt-bindings/clock/axg-audio-clkc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/meson-sm1-power.h>
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
@@ -90,7 +92,16 @@ l2: l2-cache0 {
compatible = "cache";
};
};
-
+
+ arm-pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
--
2.34.1
Powered by blists - more mailing lists