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Message-ID: <CAMuHMdUU0AiMjP2fR4vYMbkBMqbj-v4L7DdzCDaZ9P8tS97h+g@mail.gmail.com>
Date: Mon, 7 Feb 2022 17:12:51 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
Cc: Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/6] ARM: dts: r9a06g032: Add the watchdog nodes
Hi Jean-Jacques,
On Fri, Feb 4, 2022 at 5:18 PM Jean-Jacques Hiblot
<jjhiblot@...phandler.com> wrote:
> This SOC includes 2 watchdog controllers (one per A7 core).
>
> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -184,6 +184,22 @@ gic: interrupt-controller@...01000 {
> interrupts =
> <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> +
> + wdt0: watchdog@...08000 {
Please insert these nodes before the system-controller@...0c000
node, to preserve sort order (by unit address).
> + compatible = "renesas,rzn1-wdt";
"renesas,r9a06g032-wdt", "renesas,rzn1-wdt"
as per my comments on the DT bindings patch.
> + reg = <0x40008000 0x1000>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> + status = "disabled";
> + };
> +
> + wdt1: watchdog@...09000 {
> + compatible = "renesas,rzn1-wdt";
> + reg = <0x40009000 0x1000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> + status = "disabled";
> + };
> };
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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