linux-kernel - Re: [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block

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Message-ID: <dcbf28db-d47a-a2e1-dae1-48f17f9a703a@tambre.ee>
Date:   Mon, 7 Feb 2022 08:47:26 +0200
From:   Raul Tambre <raul@...bre.ee>
To:     Vidya Sagar <vidyas@...dia.com>, bhelgaas@...gle.com,
        lorenzo.pieralisi@....com, robh+dt@...nel.org,
        thierry.reding@...il.com, jonathanh@...dia.com
Cc:     kishon@...com, vkoul@...nel.org, kw@...ux.com,
        krzysztof.kozlowski@...onical.com, p.zabel@...gutronix.de,
        mperttunen@...dia.com, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
        kthota@...dia.com, mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234
 P2U block

On 2022-02-05 18:21, Vidya Sagar wrote:
> Subject:
> [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
> From:
> Vidya Sagar <vidyas@...dia.com>
> Date:
> 2022-02-05, 18:21
> 
> To:
> <bhelgaas@...gle.com>, <lorenzo.pieralisi@....com>, 
> <robh+dt@...nel.org>, <thierry.reding@...il.com>, <jonathanh@...dia.com>
> CC:
> <kishon@...com>, <vkoul@...nel.org>, <kw@...ux.com>, 
> <krzysztof.kozlowski@...onical.com>, <p.zabel@...gutronix.de>, 
> <mperttunen@...dia.com>, <linux-pci@...r.kernel.org>, 
> <devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>, 
> <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>, 
> <kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>, 
> <sagar.tv@...il.com>
> 
> 
> Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
> module instantiated once for each PCIe lane between Synopsys DesignWare
> core based PCIe IP and Universal PHY block.
> 
> Signed-off-by: Vidya Sagar<vidyas@...dia.com>
> ---
>   .../bindings/phy/phy-tegra194-p2u.yaml          | 17 +++++++++++++----
>   1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
> index 9a89d05efbda..6ba1f69b1126 100644
> --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
> @@ -4,7 +4,7 @@
>   $id:"http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
>   $schema:"http://devicetree.org/meta-schemas/core.yaml#"
>   
> -title: NVIDIA Tegra194 P2U binding
> +title: NVIDIA Tegra194 & Tegra234 P2U binding
>   
>   maintainers:
>     - Thierry Reding<treding@...dia.com>
> @@ -12,13 +12,17 @@ maintainers:
>   description: >
>     Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
>     Speed) each interfacing with 12 and 8 P2U instances respectively.
> +  Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet)

typo: namely