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Message-ID: <20220208183511.2925304-4-jjhiblot@traphandler.com>
Date: Tue, 8 Feb 2022 19:35:07 +0100
From: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
To: <linux-renesas-soc@...r.kernel.org>, <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>
CC: Jean-Jacques Hiblot <jjhiblot@...phandler.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v2 3/6] ARM: dts: r9a06g032: Add the watchdog nodes
This SOC includes 2 watchdog controllers (one per A7 core).
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index c47896e4ab58..c5659db1581b 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -66,6 +66,22 @@ soc {
interrupt-parent = <&gic>;
ranges;
+ wdt0: watchdog@...08000 {
+ compatible = "renesas,r9a06g032-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@...09000 {
+ compatible = "renesas,r9a06g032-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
sysctrl: system-controller@...0c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;
--
2.25.1
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