[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220208105646.226623-1-tudor.ambarus@microchip.com>
Date: Tue, 8 Feb 2022 12:56:46 +0200
From: Tudor Ambarus <tudor.ambarus@...rochip.com>
To: <nicolas.ferre@...rochip.com>, <claudiu.beznea@...rochip.com>,
<alexandre.belloni@...tlin.com>
CC: <robh+dt@...nel.org>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<kavyasree.kotagiri@...rochip.com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>
Subject: [PATCH v4] ARM: dts: at91: sama7g5: Add crypto nodes
Describe and enable the AES, SHA and TDES crypto IPs. Tested with the
extra run-time self tests of the registered crypto algorithms.
Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
v4: use the generic "crypto" node name for all the crypto nodes,
as recommended by the DT specification. Add Claudiu's R-b tag.
v3: remove explicit status = "okay", as it's already the default case
when not specified at all.
v2:
- add label to the tdes node
- update commit description and specify testing method
- put clocks and clock-names properties before dmas and dma-names
because the clocks are mandatory, while DMA is optional for TDES and SHA
arch/arm/boot/dts/sama7g5.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 7972cb8c2562..2453a6901313 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -393,6 +393,27 @@ pit64b1: timer@...04000 {
clock-names = "pclk", "gclk";
};
+ aes: crypto@...10000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0xe1810000 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
+ clock-names = "aes_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ };
+
+ sha: crypto@...14000 {
+ compatible = "atmel,at91sam9g46-sha";
+ reg = <0xe1814000 0x100>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
+ clock-names = "sha_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
+ dma-names = "tx";
+ };
+
flx0: flexcom@...18000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe1818000 0x200>;
@@ -475,6 +496,17 @@ trng: rng@...10000 {
status = "disabled";
};
+ tdes: crypto@...14000 {
+ compatible = "atmel,at91sam9g46-tdes";
+ reg = <0xe2014000 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
+ clock-names = "tdes_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
+ <&dma0 AT91_XDMAC_DT_PERID(53)>;
+ dma-names = "tx", "rx";
+ };
+
flx4: flexcom@...18000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe2018000 0x200>;
--
2.25.1
Powered by blists - more mailing lists