linux-kernel - Re: [PATCH v7 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 8 Feb 2022 19:16:52 +0800
From:   hammer hsieh <hammerh0314@...il.com>
To:     Jiri Slaby <jirislaby@...nel.org>
Cc:     Greg KH <gregkh@...uxfoundation.org>, robh+dt@...nel.org,
        linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, p.zabel@...gutronix.de,
        wells.lu@...plus.com, "hammer.hsieh" <hammer.hsieh@...plus.com>
Subject: Re: [PATCH v7 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver

Jiri Slaby <jirislaby@...nel.org> 於 2022年2月8日 週二 下午2:27寫道：
>
> Hi,
>
> On 07. 02. 22, 6:58, Hammer Hsieh wrote:
> > +static void sunplus_shutdown(struct uart_port *port)
> > +{
> > +     unsigned long flags;
> > +     unsigned int isc;
> > +
> > +     spin_lock_irqsave(&port->lock, flags);
> > +
> > +     isc = readl(port->membase + SUP_UART_ISC);
> > +     isc &= ~(SUP_UART_ISC_RXM | SUP_UART_ISC_TXM);
>
> Is this correct? I mean: will the SUP_UART_ISC read contain the control
> bits, not only status bits?
>

I assume reviewers don't like writel(0,xxx).
So I use definition to let the code easy to read.
The purpose is to clear all interrupt.
Bit[3:0] status bit only for read, write 1 or 0 no effect.

> > +     writel(isc, port->membase + SUP_UART_ISC);
> > +
> > +     spin_unlock_irqrestore(&port->lock, flags);
> > +
> > +     free_irq(port->irq, port);
>
> I am still waiting for explanation why this is safe with respect to
> posted writes.
>

Actually I'm not IC designer, not expert for bus design.
About data incoherence issue between memory bus and peripheral bus.
In case of AXI bus, use non-posted write can avoid data incoherence issue.
What if in case of posted write:
Send a specific command after last write command.
SDCTRL identify specific command, means previous write command done.
Then send interrupt signal to interrupt controller.
And then interrupt controller send done signal to Master.
Master receive done signal, means write command done.
Then issue a interrupt or proceed next write command.

IC designer told us no problem, and as a uart driver maintainer.
It is not my concern, but glad you ask.
Let me have chance to know it from IC designer.

> regards,
> --
> js
> suse labs