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Message-ID: <73b30627-2908-8472-01db-d07e176ce129@collabora.com>
Date: Tue, 8 Feb 2022 14:05:30 +0100
From: Andrzej Pietrasiewicz <andrzej.p@...labora.com>
To: Brian Norris <briannorris@...omium.org>,
Daniel Vetter <daniel@...ll.ch>,
David Airlie <airlied@...ux.ie>,
Heiko Stübner <heiko@...ech.de>
Cc: Sandy Huang <hjc@...k-chips.com>, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
stable@...r.kernel.org, Mark Yao <markyao0591@...il.com>
Subject: Re: [PATCH] drm/rockchip: vop: Correct RK3399 VOP register fields
Hi Brian,
Sorry about the delay.
W dniu 20.01.2022 o 01:11, Brian Norris pisze:
> Commit 7707f7227f09 ("drm/rockchip: Add support for afbc") switched up
> the rk3399_vop_big[] register windows, but it did so incorrectly.
>
> The biggest problem is in rk3288_win23_data[] vs.
> rk3368_win23_data[] .format field:
>
> RK3288's format: VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1)
> RK3368's format: VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5)
>
> Bits 5:6 (i.e., shift 5, mask 0x3) are correct for RK3399, according to
> the TRM.
>
> There are a few other small differences between the 3288 and 3368
> definitions that were swapped in commit 7707f7227f09. I reviewed them to
> the best of my ability according to the RK3399 TRM and fixed them up.
>
> This fixes IOMMU issues (and display errors) when testing with BG24
> color formats.
>
> Fixes: 7707f7227f09 ("drm/rockchip: Add support for afbc")
> Cc: Andrzej Pietrasiewicz <andrzej.p@...labora.com>
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Brian Norris <briannorris@...omium.org>
Tested-by: Andrzej Pietrasiewicz <andrzej.p@...labora.com>
> ---
> I'd appreciate notes or testing from Andrzej, since I'm not sure how he
> tested his original AFBC work.
>
> drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index 1f7353f0684a..798b542e5916 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -902,6 +902,7 @@ static const struct vop_win_phy rk3399_win01_data = {
> .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
> .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
> + .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
> .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
> .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
> .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
> @@ -912,6 +913,7 @@ static const struct vop_win_phy rk3399_win01_data = {
> .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
> .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
> .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
> + .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
> };
>
> /*
> @@ -922,11 +924,11 @@ static const struct vop_win_phy rk3399_win01_data = {
> static const struct vop_win_data rk3399_vop_win_data[] = {
> { .base = 0x00, .phy = &rk3399_win01_data,
> .type = DRM_PLANE_TYPE_PRIMARY },
> - { .base = 0x40, .phy = &rk3288_win01_data,
> + { .base = 0x40, .phy = &rk3368_win01_data,
> .type = DRM_PLANE_TYPE_OVERLAY },
> - { .base = 0x00, .phy = &rk3288_win23_data,
> + { .base = 0x00, .phy = &rk3368_win23_data,
> .type = DRM_PLANE_TYPE_OVERLAY },
> - { .base = 0x50, .phy = &rk3288_win23_data,
> + { .base = 0x50, .phy = &rk3368_win23_data,
> .type = DRM_PLANE_TYPE_CURSOR },
> };
>
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