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Message-ID: <20220209063426.ckefdtpfroj5zsad@vireshk-i7> Date: Wed, 9 Feb 2022 12:04:26 +0530 From: Viresh Kumar <viresh.kumar@...aro.org> To: Luca Weiss <luca@...tu.xyz> Cc: linux-arm-msm@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org, Andy Gross <agross@...nel.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, Ilia Lin <ilia.lin@...nel.org>, "Rafael J. Wysocki" <rafael@...nel.org>, Ansuel Smith <ansuelsmth@...il.com>, Sricharan R <sricharan@...eaurora.org>, linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH] cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse On 30-01-22, 12:45, Luca Weiss wrote: > The fuse consists of 64 bits, with this statement we're supposed to get > the upper 32 bits but it actually read out of bounds and got 0 instead > of the desired value which lead to the "PVS bin not set." codepath being > run resetting our pvs value. > > Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") > Signed-off-by: Luca Weiss <luca@...tu.xyz> > --- > drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index d1744b5d9619..6dfa86971a75 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -130,7 +130,7 @@ static void get_krait_bin_format_b(struct device *cpu_dev, > } > > /* Check PVS_BLOW_STATUS */ > - pte_efuse = *(((u32 *)buf) + 4); > + pte_efuse = *(((u32 *)buf) + 1); > pte_efuse &= BIT(21); > if (pte_efuse) { > dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); Applied. Thanks. -- viresh
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