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Message-ID: <CAMuHMdWPA+8CS371Ekx_d3Muze4CzgxwdrHO_jRg7+Vc+B+U_A@mail.gmail.com>
Date: Wed, 9 Feb 2022 09:33:04 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
Cc: Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 3/6] ARM: dts: r9a06g032: Add the watchdog nodes
Hi Jean-Jacques,
On Tue, Feb 8, 2022 at 7:35 PM Jean-Jacques Hiblot
<jjhiblot@...phandler.com> wrote:
> This SOC includes 2 watchdog controllers (one per A7 core).
>
> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@...phandler.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -66,6 +66,22 @@ soc {
> interrupt-parent = <&gic>;
> ranges;
>
> + wdt0: watchdog@...08000 {
> + compatible = "renesas,r9a06g032-wdt";
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
> + reg = <0x40008000 0x1000>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> + status = "disabled";
> + };
> +
> + wdt1: watchdog@...09000 {
> + compatible = "renesas,r9a06g032-wdt";
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
> + reg = <0x40009000 0x1000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> + status = "disabled";
> + };
> +
> sysctrl: system-controller@...0c000 {
> compatible = "renesas,r9a06g032-sysctrl";
> reg = <0x4000c000 0x1000>;
> --
> 2.25.1
>
--
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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