linux-kernel - [PATCH 1/2] ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 series

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Date:   Wed, 9 Feb 2022 11:48:48 +0100
From:   Fabrice Gasnier <fabrice.gasnier@...s.st.com>
To:     <alexandre.torgue@...s.st.com>, <robh+dt@...nel.org>
CC:     <olivier.moysan@...s.st.com>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <fabrice.gasnier@...s.st.com>
Subject: [PATCH 1/2] ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 series

Several unused "timer" are duplicate nodes of "timers" nodes.
There are two dt-schemas:
- timer/st,stm32-timer.yaml: A timer is needed on STM32F7 series, on all
  boards, to act as clockevent.
- mfd/st,stm32-timers.yaml: Timers can be used for other purpose.

By default, timer5 is left enabled to be used as clockevent. Remove all
other timer clockevent nodes that are currently unused and duplicated.

This removes several messages: Warning (unique_unit_address): /soc/timer@..
duplicate unit-address (also used in node /soc/timers@...)

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
---
 arch/arm/boot/dts/stm32f746.dtsi | 40 ----------------------------------------
 1 file changed, 40 deletions(-)

diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 014b416..a4f5c6a 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -75,14 +75,6 @@
 	};
 
 	soc {
-		timer2: timer@...00000 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000000 0x400>;
-			interrupts = <28>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
-			status = "disabled";
-		};
-
 		timers2: timers@...00000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -105,14 +97,6 @@
 			};
 		};
 
-		timer3: timer@...00400 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000400 0x400>;
-			interrupts = <29>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
-			status = "disabled";
-		};
-
 		timers3: timers@...00400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -135,14 +119,6 @@
 			};
 		};
 
-		timer4: timer@...00800 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000800 0x400>;
-			interrupts = <30>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
-			status = "disabled";
-		};
-
 		timers4: timers@...00800 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -194,14 +170,6 @@
 			};
 		};
 
-		timer6: timer@...01000 {
-			compatible = "st,stm32-timer";
-			reg = <0x40001000 0x400>;
-			interrupts = <54>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
-			status = "disabled";
-		};
-
 		timers6: timers@...01000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -218,14 +186,6 @@
 			};
 		};
 
-		timer7: timer@...01400 {
-			compatible = "st,stm32-timer";
-			reg = <0x40001400 0x400>;
-			interrupts = <55>;
-			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
-			status = "disabled";
-		};
-
 		timers7: timers@...01400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.7.4