linux-kernel - [PATCH v6 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

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Message-Id: <20220209123800.269774-12-heiko@sntech.de>
Date:   Wed,  9 Feb 2022 13:37:57 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     palmer@...belt.com, paul.walmsley@...ive.com, aou@...s.berkeley.edu
Cc:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, robh+dt@...nel.org, wefu@...hat.com,
        liush@...winnertech.com, guoren@...nel.org, atishp@...shpatra.org,
        anup@...infault.org, drew@...gleboard.org, hch@....de,
        arnd@...db.de, wens@...e.org, maxime@...no.tech,
        gfavor@...tanamicro.com, andrea.mondelli@...wei.com,
        behrensj@....edu, xinhaoqu@...wei.com, huffman@...ence.com,
        mick@....forth.gr, allen.baum@...erantotech.com,
        jscheid@...tanamicro.com, rtrauben@...il.com, samuel@...lland.org,
        cmuellner@...ux.com, philipp.tomsich@...ll.eu,
        Heiko Stuebner <heiko@...ech.de>
Subject: [PATCH v6 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

From: Wei Fu <wefu@...hat.com>

Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
in the DT mmu node. Update dt-bindings related property here.

Signed-off-by: Wei Fu <wefu@...hat.com>
Co-developed-by: Guo Ren <guoren@...nel.org>
Signed-off-by: Guo Ren <guoren@...nel.org>
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Cc: Anup Patel <anup@...infault.org>
Cc: Palmer Dabbelt <palmer@...belt.com>
Cc: Rob Herring <robh+dt@...nel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index aa5fb64d57eb..6b5fc5d7a901 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,16 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  riscv,mmu:
+    description:
+      Describes the CPU's MMU Standard Extensions support.
+      These values originate from the RISC-V Privileged
+      Specification document, available from
+      https://riscv.org/specifications/
+    $ref: '/schemas/types.yaml#/definitions/string'
+    enum:
+      - riscv,svpbmt
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture
-- 
2.30.2