linux-kernel - Re: [PATCH] riscv: fix build with binutils 2.38

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Message-ID: <mhng-f5101f2f-eb08-4e20-8cb3-b7d267ba25bc@palmer-ri-x1c9>
Date:   Thu, 10 Feb 2022 09:40:22 -0800 (PST)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     aurelien@...el32.net
CC:     linux-kernel@...r.kernel.org, aurelien@...el32.net,
        stable@...r.kernel.org, Kito Cheng <kito.cheng@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        aou@...s.berkeley.edu,
        linux-riscv@...ts.infradead.org (open list:RISC-V ARCHITECTURE)
Subject:     Re: [PATCH] riscv: fix build with binutils 2.38

On Wed, 26 Jan 2022 09:14:42 PST (-0800), aurelien@...el32.net wrote:
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> this causes the following build failure:
>
>   CC      arch/riscv/kernel/vdso/vgettimeofday.o
>   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
>   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
>   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
>   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
>   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
>
> The fix is to specify those extensions explicitely in -march. However as
> older binutils version do not support this, we first need to detect
> that.
>
> Cc: stable@...r.kernel.org # 4.15+
> Cc: Kito Cheng <kito.cheng@...il.com>
> Signed-off-by: Aurelien Jarno <aurelien@...el32.net>
> ---
>  arch/riscv/Makefile | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 8a107ed18b0d..7d81102cffd4 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
>  riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
>  riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
>  riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
> +
> +# Newer binutils versions default to ISA spec version 20191213 which moves some
> +# instructions from the I extension to the Zicsr and Zifencei extensions.
> +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> +
>  KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
>  KBUILD_AFLAGS += -march=$(riscv-march-y)

Thanks, this is on fixes.  It's CC stable, but doesn't have a "Fixes" 
tag -- I did that on purpose as this isn't really fixing a bug in Linux 
so I'm not sure it's right to point at a particular patch, but I'm not 
sure how that will play with the stable tree.