linux-kernel - Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220210193459.nl6baranvmqs46bi@coastal>
Date:   Thu, 10 Feb 2022 13:34:59 -0600
From:   Nishanth Menon <nm@...com>
To:     Marc Zyngier <maz@...nel.org>
CC:     Vignesh Raghavendra <vigneshr@...com>,
        Tero Kristo <kristo@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Santosh Shilimkar <ssantosh@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC

On 19:10-20220209, Marc Zyngier wrote:
[...]

> > +&cbass_main {
> > +	gic500: interrupt-controller@...0000 {
> > +		compatible = "arm,gic-v3";
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
> > +		      <0x00 0x01880000 0x00 0xC0000>;	/* GICR */
> 
> Usual rant: you are missing the GICC, GICH and GICV regions
> that are implemented by the CPU. Cortex-A53 implements them
> (they are not optional), so please describe them.
> 


-ECONFUSED. TRM for GIC500 refers to just GICD, GICR and ITS range[1].

Same thing is indicated by Generic Interrupt Controller Architecture
Specification[2] See table 1-1 (page 23).

I think you are expecting GICV3's backward compatibility mode (Table 1-2
in page 24), But in K3 architecture, are_option meant for backward
compatibility is set to true (aka no backward compatibility). I think
this did popup sometime back as well (first k3 SoC)[3]. I think the more
clearer description is available in [4].

I believe the argumentation that GICC/H/V is mandatory for A53 if GIC500
is used is not accurate. Please correct me if I am mistaken.


[1] https://developer.arm.com/documentation/ddi0516/e/programmers-model/the-gic-500-register-map?lang=en
[2] https://developer.arm.com/documentation/ihi0069/d
[3] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20180607233853.p7iw7nlxxuyi66og@kahuna/
[4] https://developer.arm.com/documentation/ddi0516/e/functional-description/operation/backwards-compatibility?lang=en

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D