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Message-ID: <42e27aa2-afb6-656d-9b56-c822a8c510ad@quicinc.com>
Date: Thu, 10 Feb 2022 19:57:49 +0530
From: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
To: Stephen Boyd <swboyd@...omium.org>, <agross@...nel.org>,
<bjorn.andersson@...aro.org>, <devicetree@...r.kernel.org>,
<dianders@...omium.org>, <judyhsiao@...omium.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<robh+dt@...nel.org>, <rohitkr@...eaurora.org>,
<srinivas.kandagatla@...aro.org>
CC: Venkata Prasad Potturu <quic_potturu@...cinc.com>
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sc7280: add lpass lpi pin
controller node
On 2/10/2022 5:35 AM, Stephen Boyd wrote:
Thanks for Your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2022-02-09 06:01:21)
>> On 2/9/2022 2:41 AM, Stephen Boyd wrote:
>>> Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:13)
>>>> + data {
>>>> + pins = "gpio7";
>>>> + function = "dmic1_data";
>>>> + drive-strength = <8>;
>>>> + input-enable;
>>>> + };
>>>> + };
>>>> +
>>>> + dmic01_sleep: dmic01-sleep-pins {
>>>> + clk {
>>>> + pins = "gpio6";
>>>> + function = "dmic1_clk";
>>>> + drive-strength = <2>;
>>>> + bias-disable;
>>>> + output-low;
>>>> + };
>>>> +
>>>> + data {
>>>> + pins = "gpio7";
>>>> + function = "dmic1_data";
>>>> + drive-strength = <2>;
>>>> + pull-down;
>>>> + input-enable;
>>> Why does input-enable matter? It's not a gpio.
>> Actually the same is fallowed in sm8250.dtsi. Verified without it and
>> working fine. Need take call on it.
> Is that because the pin is already an input by default? What does gpio
> debugfs say for this pin? Does it also work if you make it
> output-low/output-high here? I thought that the gpio itself isn't muxed
> out to the pad unless the function is "gpio" so I hope the input/output
> settings have no effect here.
Pin is in by default. debugfs says
gpio7 : in 1 8mA no pull
verified in downstream code also. Same is followed there also.
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