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Message-ID: <AS8PR04MB8676C19FBD01547BDF80CFC68C309@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Fri, 11 Feb 2022 02:05:24 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management support
> -----Original Message-----
> From: Bjorn Helgaas <helgaas@...nel.org>
> Sent: 2022年2月11日 6:05
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: l.stach@...gutronix.de; bhelgaas@...gle.com;
> lorenzo.pieralisi@....com; shawnguo@...nel.org; linux-pci@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> kernel@...gutronix.de; dl-linux-imx <linux-imx@....com>
> Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management
> support
>
> On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Bjorn Helgaas <helgaas@...nel.org>
> > > Sent: 2022年2月9日 23:37
> > > To: Hongxing Zhu <hongxing.zhu@....com>
> > > Cc: l.stach@...gutronix.de; bhelgaas@...gle.com;
> > > lorenzo.pieralisi@....com; shawnguo@...nel.org;
> > > linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> > > linux-kernel@...r.kernel.org; kernel@...gutronix.de; dl-linux-imx
> > > <linux-imx@....com>
> > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power
> > > management support
> > >
> > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote:
> > > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2
> > > > exit by the reset mechanism.
> > > > Enable the i.MX6QP PCIe suspend/resume operations support.
>
> > > What does "L2 exit by reset mechanism" mean? Is this an
> > > i.MX6-specific thing? If not, can you point me to the relevant part
> > > of the PCIe spec?
> >
> > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the
> > self-reset mechanism. Thus, it can't reset itself to an initialized
> > stat when link exit from the L2 or L3 stats. i.MX6QP PCIe has the
> > self-reset mechanism, and it can reset itself when link exit from L2
> > or L3 stats. The commit description might not accurate. How about
> > change them to "i.MX6QP PCIe supports the RESET logic, thus it can
> > reset itself to the initialized stat when exit from L2 or L3 stats."
>
> s/stat/state/
Thanks for your quickly reply.
Got that, would be changed later.
>
> Ugh, I have all sorts of questions now, but I don't think I want to know much
> more about this ;)
>
> Seems like this device requires software assist when bringing the link out of L2
> or L3. Is that allowed per PCIe spec, or is this an erratum?
>
> Does this mean the driver needs to be involved when we take a device out of
> D3 (where the link was in L2 or L3)?
Yes, the SW should be involved when bringing the link out of L2 or L3.
I looked through the SPEC, didn't find that they are forbidden by SPEC.
It might be a design limitation, I think.
Best Regards
Richard Zhu
>
> Bjorn
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