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Message-ID: <7eca7a1d-a5a2-2aab-b3cf-5d83cb8ccf4f@arm.com>
Date: Fri, 11 Feb 2022 16:31:40 +0000
From: German Gomez <german.gomez@....com>
To: Ali Saidi <alisaidi@...zon.com>, leo.yan@...aro.org
Cc: acme@...nel.org, alexander.shishkin@...ux.intel.com,
andrew.kilroy@....com, benh@...nel.crashing.org,
james.clark@....com, john.garry@...wei.com, jolsa@...hat.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, mark.rutland@....com,
mathieu.poirier@...aro.org, mingo@...hat.com, namhyung@...nel.org,
peterz@...radead.org, will@...nel.org
Subject: Re: [PATCH 2/2] perf arm-spe: Parse more SPE fields and store source
Hi Ali,
On 28/01/2022 21:02, Ali Saidi wrote:
> Hi German,
>
> On 28/01/2022 19:20, German Gomez wrote:
>> Hi Ali,
>>
>> [...]
>>> };
>>>
>>> enum arm_spe_op_type {
>>> ARM_SPE_LD = 1 << 0,
>>> ARM_SPE_ST = 1 << 1,
>>> + ARM_SPE_LDST_EXCL = 1 << 2,
>>> + ARM_SPE_LDST_ATOMIC = 1 << 3,
>>> + ARM_SPE_LDST_ACQREL = 1 << 4,
Wondering if we can store this in perf_sample->flags. The values are
defined in "util/event.h" (PERF_IP_*). Maybe we can extend it to allow
doing "sample->flags = PERF_LDST_FLAG_LD | PERF_LDST_FLAG_ATOMIC" and
such.
@Leo do you think that could work?
>>> + ARM_SPE_BR = 1 << 5,
>>> + ARM_SPE_BR_COND = 1 << 6,
>>> + ARM_SPE_BR_IND = 1 << 7,
Seems like we can store BR_COND in the existing "branch-miss" event
(--itrace=b) with:
sample->flags = PERF_IP_FLAG_BRANCH;
sample->flags |= PERF_IP_FLAG_CONDITIONAL;
and/or
sample->flags |= PERF_IP_FLAG_INDIRECT;
PERF_IP_FLAG_INDIRECT doesn't exist yet but we can probably add it.
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