linux-kernel - [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220214112619.219761-6-tianfei.zhang@intel.com>
Date:   Mon, 14 Feb 2022 06:26:17 -0500
From:   Tianfei zhang <tianfei.zhang@...el.com>
To:     hao.wu@...el.com, trix@...hat.com, mdf@...nel.org,
        yilun.xu@...el.com, linux-fpga@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     corbet@....net, Matthew Gerlach <matthew.gerlach@...ux.intel.com>,
        Tianfei Zhang <tianfei.zhang@...el.com>
Subject: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>

Not all FPGA designs managed by the DFL driver have a port.
In these cases, don't write the Port Access Control register
when enabling SRIOV.

Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Signed-off-by: Tianfei Zhang <tianfei.zhang@...el.com>
---
 drivers/fpga/dfl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index cfc539a656f0..a5263ac258c5 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
 	int ret = 0, port_count = 0;
 
 	mutex_lock(&cdev->lock);
+	if (list_empty(&cdev->port_dev_list))
+		goto done;
 
 	list_for_each_entry(pdata, &cdev->port_dev_list, node) {
 		if (pdata->dev)
-- 
2.17.1